mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-15 20:10:28 +00:00
19 lines
265 B
Text
19 lines
265 B
Text
read_verilog <<EOT
|
|
module top(inout io);
|
|
wire in;
|
|
wire t;
|
|
wire o;
|
|
|
|
IOBUF IOBUF(
|
|
.I(in),
|
|
.T(t),
|
|
.IO(io),
|
|
.O(o)
|
|
);
|
|
endmodule
|
|
EOT
|
|
|
|
synth_analogdevices
|
|
cd top
|
|
select -assert-count 1 t:IOBUF
|
|
select -assert-none t:* t:IOBUF %d
|