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42 lines
958 B
Verilog
42 lines
958 B
Verilog
module test(D, C, E, R, Q);
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parameter [0:0] CLKPOL = 0;
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parameter [0:0] ENABLE_EN = 0;
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parameter [0:0] RESET_EN = 0;
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parameter [0:0] RESET_VAL = 0;
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parameter [0:0] RESET_SYN = 0;
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(* gentb_clock *)
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input D, C, E, R;
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output Q;
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wire gated_reset = R & RESET_EN;
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wire gated_enable = E | ~ENABLE_EN;
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reg posedge_q, negedge_q, posedge_sq, negedge_sq;
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always @(posedge C, posedge gated_reset)
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if (gated_reset)
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posedge_q <= RESET_VAL;
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else if (gated_enable)
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posedge_q <= D;
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always @(negedge C, posedge gated_reset)
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if (gated_reset)
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negedge_q <= RESET_VAL;
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else if (gated_enable)
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negedge_q <= D;
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always @(posedge C)
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if (gated_reset)
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posedge_sq <= RESET_VAL;
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else if (gated_enable)
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posedge_sq <= D;
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always @(negedge C)
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if (gated_reset)
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negedge_sq <= RESET_VAL;
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else if (gated_enable)
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negedge_sq <= D;
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assign Q = RESET_SYN ? (CLKPOL ? posedge_sq : negedge_sq) : (CLKPOL ? posedge_q : negedge_q);
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endmodule
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