mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
8 lines
164 B
Verilog
8 lines
164 B
Verilog
(* blackbox *)
|
|
module AND(input [7:0] A, B, output [7:0] Y);
|
|
endmodule
|
|
|
|
(* blackbox *)
|
|
module ALU(input [7:0] A, B, output [7:0] Y);
|
|
parameter MODE = "";
|
|
endmodule
|