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24 lines
620 B
Verilog
24 lines
620 B
Verilog
// expect-wr-ports 1
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// expect-rd-ports 2
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module test(clk, rd_addr, rd_data, cp_addr, wr_addr, wr_en, wr_data);
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input clk;
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input [3:0] rd_addr;
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output reg [31:0] rd_data;
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input [3:0] cp_addr, wr_addr, wr_en;
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input [31:0] wr_data;
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reg [31:0] mem [0:15];
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always @(posedge clk) begin
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mem[wr_addr][ 7: 0] <= wr_en[0] ? wr_data[ 7: 0] : mem[cp_addr][ 7: 0];
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mem[wr_addr][15: 8] <= wr_en[1] ? wr_data[15: 8] : mem[cp_addr][15: 8];
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mem[wr_addr][23:16] <= wr_en[2] ? wr_data[23:16] : mem[cp_addr][23:16];
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mem[wr_addr][31:24] <= wr_en[3] ? wr_data[31:24] : mem[cp_addr][31:24];
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rd_data <= mem[rd_addr];
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end
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endmodule
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