mirror of
https://github.com/YosysHQ/yosys
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411 lines
9.3 KiB
Systemverilog
411 lines
9.3 KiB
Systemverilog
// ---------------------------------------
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(* abc9_lut=1, lib_whitebox *)
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module LUT4(input A, B, C, D, output Z);
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parameter [15:0] INIT = 16'h0000;
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wire [7:0] s3 = D ? INIT[15:8] : INIT[7:0];
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wire [3:0] s2 = C ? s3[ 7:4] : s3[3:0];
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wire [1:0] s1 = B ? s2[ 3:2] : s2[1:0];
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assign Z = A ? s1[1] : s1[0];
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specify
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(A => Z) = 141;
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(B => Z) = 275;
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(C => Z) = 379;
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(D => Z) = 379;
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endspecify
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// cost of 5-input LUTs and is not intended to be instantiated
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// LUT5 = 2x LUT4 + PFUMX
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(* abc9_lut=2 *)
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module \$__ABC9_LUT5 (input M0, D, C, B, A, output Z);
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specify
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(M0 => Z) = 151;
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(D => Z) = 239;
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(C => Z) = 373;
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(B => Z) = 477;
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(A => Z) = 477;
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endspecify
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// of 6-input LUTs and is not intended to be instantiated
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// LUT6 = 2x LUT5 + MUX2
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(* abc9_lut=4 *)
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module \$__ABC9_LUT6 (input M1, M0, D, C, B, A, output Z);
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specify
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(M1 => Z) = 148;
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(M0 => Z) = 292;
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(D => Z) = 380;
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(C => Z) = 514;
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(B => Z) = 618;
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(A => Z) = 618;
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endspecify
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endmodule
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// This is a placeholder for ABC9 to extract the area/delay
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// of 7-input LUTs and is not intended to be instantiated
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// LUT7 = 2x LUT6 + MUX2
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(* abc9_lut=8 *)
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module \$__ABC9_LUT7 (input M2, M1, M0, D, C, B, A, output Z);
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specify
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(M2 => Z) = 148;
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(M1 => Z) = 289;
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(M0 => Z) = 433;
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(D => Z) = 521;
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(C => Z) = 655;
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(B => Z) = 759;
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(A => Z) = 759;
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endspecify
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endmodule
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// ---------------------------------------
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(* abc9_box, lib_whitebox *)
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module L6MUX21 (input D0, D1, SD, output Z);
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assign Z = SD ? D1 : D0;
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specify
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(D0 => Z) = 140;
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(D1 => Z) = 141;
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(SD => Z) = 148;
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endspecify
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endmodule
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// ---------------------------------------
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module TRELLIS_RAM16X2 (
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input DI0, DI1,
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input WAD0, WAD1, WAD2, WAD3,
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input WRE, WCK,
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input RAD0, RAD1, RAD2, RAD3,
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output DO0, DO1
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter INITVAL_0 = 16'h0000;
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parameter INITVAL_1 = 16'h0000;
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reg [1:0] mem[15:0];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= {INITVAL_1[i], INITVAL_0[i]};
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end
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wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
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reg muxwre;
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always @(*)
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case (WREMUX)
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"1": muxwre = 1'b1;
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"0": muxwre = 1'b0;
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"INV": muxwre = ~WRE;
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default: muxwre = WRE;
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endcase
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always @(posedge muxwck)
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if (muxwre)
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mem[{WAD3, WAD2, WAD1, WAD0}] <= {DI1, DI0};
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assign {DO1, DO0} = mem[{RAD3, RAD2, RAD1, RAD0}];
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endmodule
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// ---------------------------------------
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(* abc9_box, lib_whitebox *)
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module PFUMX (input ALUT, BLUT, C0, output Z);
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assign Z = C0 ? ALUT : BLUT;
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specify
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(ALUT => Z) = 98;
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(BLUT => Z) = 98;
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(C0 => Z) = 151;
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endspecify
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endmodule
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// ---------------------------------------
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(* abc9_box, lib_whitebox *)
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module TRELLIS_DPR16X4 (
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input [3:0] DI,
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input [3:0] WAD,
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input WRE,
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input WCK,
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input [3:0] RAD,
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter [63:0] INITVAL = 64'h0000000000000000;
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reg [3:0] mem[15:0];
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integer i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] <= INITVAL[4*i +: 4];
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end
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wire muxwck = (WCKMUX == "INV") ? ~WCK : WCK;
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reg muxwre;
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always @(*)
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case (WREMUX)
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"1": muxwre = 1'b1;
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"0": muxwre = 1'b0;
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"INV": muxwre = ~WRE;
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default: muxwre = WRE;
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endcase
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always @(posedge muxwck)
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if (muxwre)
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mem[WAD] <= DI;
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assign DO = mem[RAD];
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specify
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// TODO
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(RAD *> DO) = 0;
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endspecify
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endmodule
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// ---------------------------------------
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(* abc9_box, lib_whitebox *)
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module DPR16X4C (
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input [3:0] DI,
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input WCK, WRE,
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input [3:0] RAD,
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input [3:0] WAD,
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output [3:0] DO
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);
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// For legacy Lattice compatibility, INITIVAL is a hex
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// string rather than a numeric parameter
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parameter INITVAL = "0x0000000000000000";
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function [63:0] convert_initval;
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input [143:0] hex_initval;
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reg done;
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reg [63:0] temp;
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reg [7:0] char;
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integer i;
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begin
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done = 1'b0;
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temp = 0;
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for (i = 0; i < 16; i = i + 1) begin
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if (!done) begin
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char = hex_initval[8*i +: 8];
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if (char == "x") begin
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done = 1'b1;
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end else begin
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if (char >= "0" && char <= "9")
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temp[4*i +: 4] = char - "0";
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else if (char >= "A" && char <= "F")
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temp[4*i +: 4] = 10 + char - "A";
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else if (char >= "a" && char <= "f")
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temp[4*i +: 4] = 10 + char - "a";
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end
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end
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end
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convert_initval = temp;
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end
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endfunction
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localparam conv_initval = convert_initval(INITVAL);
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reg [3:0] ram[0:15];
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integer i;
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initial begin
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for (i = 0; i < 15; i = i + 1) begin
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ram[i] <= conv_initval[4*i +: 4];
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end
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end
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always @(posedge WCK)
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if (WRE)
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ram[WAD] <= DI;
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assign DO = ram[RAD];
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specify
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// TODO
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(RAD *> DO) = 0;
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endspecify
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endmodule
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// ---------------------------------------
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(* lib_whitebox *)
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module LUT2(input A, B, output Z);
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parameter [3:0] INIT = 4'h0;
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wire [1:0] s1 = B ? INIT[ 3:2] : INIT[1:0];
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assign Z = A ? s1[1] : s1[0];
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endmodule
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// ---------------------------------------
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`ifdef YOSYS
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(* abc9_flop=(SRMODE != "ASYNC"), abc9_box=(SRMODE == "ASYNC"), lib_whitebox *)
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`endif
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module TRELLIS_FF(input CLK, LSR, CE, DI, M, output reg Q);
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parameter GSR = "ENABLED";
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parameter [127:0] CEMUX = "1";
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parameter CLKMUX = "CLK";
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parameter LSRMUX = "LSR";
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parameter SRMODE = "LSR_OVER_CE";
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parameter REGSET = "RESET";
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parameter [127:0] LSRMODE = "LSR";
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wire muxce;
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generate
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case (CEMUX)
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"1": assign muxce = 1'b1;
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"0": assign muxce = 1'b0;
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"INV": assign muxce = ~CE;
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default: assign muxce = CE;
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endcase
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endgenerate
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wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
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wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
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wire srval;
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generate
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if (LSRMODE == "PRLD")
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assign srval = M;
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else
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assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
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endgenerate
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initial Q = srval;
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generate
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if (SRMODE == "ASYNC") begin
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always @(posedge muxclk, posedge muxlsr)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end else begin
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always @(posedge muxclk)
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if (muxlsr)
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Q <= srval;
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else if (muxce)
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Q <= DI;
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end
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endgenerate
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specify
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$setup(DI, negedge CLK &&& CLKMUX == "INV", 0);
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$setup(CE, negedge CLK &&& CLKMUX == "INV", 0);
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$setup(LSR, negedge CLK &&& CLKMUX == "INV", 0);
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$setup(DI, posedge CLK &&& CLKMUX != "INV", 0);
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$setup(CE, posedge CLK &&& CLKMUX != "INV", 0);
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$setup(LSR, posedge CLK &&& CLKMUX != "INV", 0);
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`ifndef YOSYS
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if (SRMODE == "ASYNC" && muxlsr && CLKMUX == "INV") (negedge CLK => (Q : srval)) = 0;
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if (SRMODE == "ASYNC" && muxlsr && CLKMUX != "INV") (posedge CLK => (Q : srval)) = 0;
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`else
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if (SRMODE == "ASYNC" && muxlsr) (LSR => Q) = 0; // Technically, this should be an edge sensitive path
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// but for facilitating a bypass box, let's pretend it's
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// a simple path
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`endif
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if (!muxlsr && muxce && CLKMUX == "INV") (negedge CLK => (Q : DI)) = 0;
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if (!muxlsr && muxce && CLKMUX != "INV") (posedge CLK => (Q : DI)) = 0;
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endspecify
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endmodule
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// ---------------------------------------
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(* keep *)
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module TRELLIS_IO(
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(* iopad_external_pin *)
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inout B,
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input I,
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input T,
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output O
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);
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parameter DIR = "INPUT";
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reg T_pd;
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always @(*) if (T === 1'bz) T_pd <= 1'b0; else T_pd <= T;
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generate
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if (DIR == "INPUT") begin
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assign B = 1'bz;
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assign O = B;
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end else if (DIR == "OUTPUT") begin
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assign B = T_pd ? 1'bz : I;
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assign O = 1'bx;
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end else if (DIR == "BIDIR") begin
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assign B = T_pd ? 1'bz : I;
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assign O = B;
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end else begin
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ERROR_UNKNOWN_IO_MODE error();
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end
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endgenerate
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endmodule
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// ---------------------------------------
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module INV(input A, output Z);
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assign Z = !A;
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endmodule
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// ---------------------------------------
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module TRELLIS_COMB(
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input A, B, C, D, M,
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input FCI, F1, FXA, FXB,
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input WD,
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input WAD0, WAD1, WAD2, WAD3,
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input WRE, WCK,
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output F, FCO, OFX
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);
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parameter MODE = "LOGIC";
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parameter INITVAL = 16'h0;
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parameter CCU2_INJECT1 = "NO";
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parameter WREMUX = "WRE";
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parameter IS_Z1 = 1'b0;
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generate
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if (MODE == "LOGIC") begin: mode_logic
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LUT4 #(.INIT(INITVAL)) lut4 (.A(A), .B(B), .C(C), .D(D), .Z(F));
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end else if (MODE == "CCU2") begin: mode_ccu2
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wire l4o, l2o;
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LUT4 #(.INIT(INITVAL)) lut4_0(.A(A), .B(B), .C(C), .D(D), .Z(l4o));
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LUT2 #(.INIT(INITVAL[3:0])) lut2_0(.A(A), .B(B), .Z(l2o));
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wire gated_cin_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : FCI;
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assign F = l4o ^ gated_cin_0;
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wire gated_lut2_0 = (CCU2_INJECT1 == "YES") ? 1'b0 : l2o;
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wire FCO = (~l4o & gated_lut2_0) | (l4o & FCI);
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end else if (MODE == "DPRAM") begin: mode_dpram
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reg [15:0] ram = INITVAL;
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always @(posedge WCK)
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if (WRE)
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ram[{WAD3, WAD2, WAD1, WAD0}] <= WD;
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assign F = ram[{A, C, B, D}];
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end else begin
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$error("unsupported COMB mode %s", MODE);
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end
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if (IS_Z1)
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L6MUX21 lutx_mux (.D0(FXA), .D1(FXB), .SD(M), .Z(OFX));
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else
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PFUMX lut5_mux (.ALUT(F1), .BLUT(F), .C0(M), .Z(OFX));
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endgenerate
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endmodule
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// Constants
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module VLO(output Z);
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assign Z = 1'b0;
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endmodule
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module VHI(output Z);
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assign Z = 1'b1;
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endmodule
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`ifndef NO_INCLUDES
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`include "cells_ff.vh"
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`include "cells_io.vh"
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`endif
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