mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
082cbcb4c7
The techmap rules for this target do not work in the first place (note lack of >2-input LUT mappings), and if proper support is ever added, it'd be better placed in the synth_intel_alm backend.
14 lines
901 B
Makefile
14 lines
901 B
Makefile
|
|
OBJS += techlibs/intel/synth_intel.o
|
|
|
|
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
|
|
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
|
|
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
|
|
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
|
|
$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v))
|
|
|
|
# Add the cell models and mappings for the VQM backend
|
|
families := max10 cyclone10lp cycloneiv cycloneive
|
|
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v)))
|
|
$(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v)))
|
|
#$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v))
|