mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-15 03:35:40 +00:00
579 lines
17 KiB
C++
579 lines
17 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* 2019 Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/log.h"
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#include "kernel/register.h"
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#include "kernel/rtlil.h"
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#include "kernel/sigtools.h"
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#include <algorithm>
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#include <stdio.h>
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#include <stdlib.h>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OpMuxConn {
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RTLIL::SigSpec sig;
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RTLIL::Cell *mux;
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RTLIL::Cell *op;
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int mux_port_id;
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int mux_port_offset;
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int op_outsig_offset;
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bool operator<(const OpMuxConn &other) const
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{
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if (mux != other.mux)
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return mux < other.mux;
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if (mux_port_id != other.mux_port_id)
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return mux_port_id < other.mux_port_id;
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return mux_port_offset < other.mux_port_offset;
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}
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};
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// Helper class to track additiona information about a SigSpec, like whether it is signed and the semantics of the port it is connected to
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struct ExtSigSpec {
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RTLIL::SigSpec sig;
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RTLIL::SigSpec sign;
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bool is_signed;
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TwineRef semantics;
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ExtSigSpec() {}
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ExtSigSpec(RTLIL::SigSpec s, RTLIL::SigSpec sign = RTLIL::Const(0, 1), bool is_signed = false, TwineRef semantics = Twine::Null) : sig(s), sign(sign), is_signed(is_signed), semantics(semantics) {}
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bool empty() const { return sig.empty(); }
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bool operator<(const ExtSigSpec &other) const
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{
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if (sig != other.sig)
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return sig < other.sig;
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if (sign != other.sign)
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return sign < other.sign;
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if (is_signed != other.is_signed)
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return is_signed < other.is_signed;
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return semantics < other.semantics;
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}
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bool operator==(const RTLIL::SigSpec &other) const { return (sign != RTLIL::Const(0, 1)) ? false : sig == other; }
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bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
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};
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#define FINE_BITWISE_OPS TW($_AND_), TW($_NAND_), TW($_OR_), TW($_NOR_), TW($_XOR_), TW($_XNOR_), TW($_ANDNOT_), TW($_ORNOT_)
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#define BITWISE_OPS FINE_BITWISE_OPS, TW($and), TW($or), TW($xor), TW($xnor)
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#define REDUCTION_OPS TW($reduce_and), TW($reduce_or), TW($reduce_xor), TW($reduce_xnor), TW($reduce_bool), TW($reduce_nand)
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#define LOGICAL_OPS TW($logic_and), TW($logic_or)
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#define SHIFT_OPS TW($shl), TW($shr), TW($sshl), TW($sshr), TW($shift), TW($shiftx)
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#define RELATIONAL_OPS TW($lt), TW($le), TW($eq), TW($ne), TW($eqx), TW($nex), TW($ge), TW($gt)
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bool cell_supported(RTLIL::Cell *cell)
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{
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if (cell->type.in(TW($alu))) {
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RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
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RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
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if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
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return true;
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} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, TW($add), TW($sub), TW($mul), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat))) {
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return true;
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}
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return false;
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}
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dict<TwineRef, TwineRef> mergeable_type_map;
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bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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if (mergeable_type_map.empty()) {
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mergeable_type_map.insert({TW($sub), TW($add)});
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}
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TwineRef a_type = a->type.ref();
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if (mergeable_type_map.count(a_type))
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a_type = mergeable_type_map.at(a_type);
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TwineRef b_type = b->type.ref();
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if (mergeable_type_map.count(b_type))
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b_type = mergeable_type_map.at(b_type);
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return a_type == b_type;
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}
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TwineRef decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
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{
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if (cell->type.in(TW($lt), TW($le), TW($ge), TW($gt), TW($div), TW($mod), TW($divfloor), TW($modfloor), TW($concat), SHIFT_OPS) && port_name == TW::B)
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return port_name;
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if (cell->type.in(TW($_ANDNOT_), TW($_ORNOT_)))
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return port_name;
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return Twine::Null;
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}
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RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) {
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if (cell->type == TW($alu) && port_name == TW::B)
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return cell->getPort(TW::BI);
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else if (cell->type == TW($sub) && port_name == TW::B)
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return RTLIL::Const(1, 1);
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return RTLIL::Const(0, 1);
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}
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bool decode_port_signed(RTLIL::Cell *cell, TwineRef port_name)
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{
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if (cell->type.in(BITWISE_OPS, LOGICAL_OPS))
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return false;
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auto param_signed = cell->module->design->twines.str(port_name) + "_SIGNED";
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if (cell->hasParam(param_signed))
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return cell->getParam(param_signed).as_bool();
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return false;
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}
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ExtSigSpec decode_port(RTLIL::Cell *cell, TwineRef port_name, const SigMap &sigmap)
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{
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auto sig = sigmap(cell->getPort(port_name));
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RTLIL::SigSpec sign = decode_port_sign(cell, port_name);
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TwineRef semantics = decode_port_semantics(cell, port_name);
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bool is_signed = decode_port_signed(cell, port_name);
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return ExtSigSpec(sig, sign, is_signed, semantics);
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}
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand, const SigMap &sigmap)
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{
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std::vector<ExtSigSpec> muxed_operands;
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int max_width = 0;
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for (const auto& p : ports) {
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auto op = p.op;
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TwineRef muxed_port_name = TW::A;
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if (decode_port(op, TW::A, sigmap) == operand)
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muxed_port_name = TW::B;
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auto operand = decode_port(op, muxed_port_name, sigmap);
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if (operand.sig.size() > max_width)
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max_width = operand.sig.size();
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muxed_operands.push_back(operand);
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}
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auto shared_op = ports[0].op;
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if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
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max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
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for (auto &operand : muxed_operands) {
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operand.sig.extend_u0(max_width, operand.is_signed);
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if (operand.sign != muxed_operands[0].sign)
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operand = ExtSigSpec(module->Neg(NEW_TWINE, operand.sig, operand.is_signed));
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}
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for (const auto& p : ports) {
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auto op = p.op;
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if (op == shared_op)
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continue;
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module->remove(op);
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}
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RTLIL::SigSpec mux_a = mux->getPort(TW::A);
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RTLIL::SigSpec mux_b = mux->getPort(TW::B);
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RTLIL::SigSpec mux_s = mux->getPort(TW::S);
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int conn_width = ports[0].sig.size();
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int conn_mux_offset = ports[0].mux_port_offset;
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int conn_op_offset = ports[0].op_outsig_offset;
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RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
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RTLIL::SigSpec shared_pmux_b;
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RTLIL::SigSpec shared_pmux_s;
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// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
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Wire *new_out = module->addWire(NEW_TWINE, conn_op_offset + conn_width);
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SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
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for (int i = 0; i < GetSize(ports); i++) {
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auto &p = ports[i];
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auto &op = muxed_operands[i];
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if (p.mux_port_id == GetSize(mux_s)) {
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shared_pmux_a = op.sig;
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mux_a.replace(conn_mux_offset, new_sig_out);
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} else {
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shared_pmux_s.append(mux_s[p.mux_port_id]);
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shared_pmux_b.append(op.sig);
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_mux_offset, new_sig_out);
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}
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}
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mux->setPort(TW::A, mux_a);
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mux->setPort(TW::B, mux_b);
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mux->setPort(TW::S, mux_s);
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SigSpec mux_to_oper;
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if (GetSize(shared_pmux_s) == 1) {
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mux_to_oper = module->Mux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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} else {
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mux_to_oper = module->Pmux(NEW_TWINE, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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}
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if (shared_op->type.in(TW($alu))) {
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shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out)));
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shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out)));
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}
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bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
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shared_op->setPort(TW::Y, new_out);
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if (!is_fine)
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shared_op->setParam(ID::Y_WIDTH, GetSize(new_out));
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if (decode_port(shared_op, TW::A, sigmap) == operand) {
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shared_op->setPort(TW::B, mux_to_oper);
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if (!is_fine)
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shared_op->setParam(ID::B_WIDTH, max_width);
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} else {
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shared_op->setPort(TW::A, mux_to_oper);
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if (!is_fine)
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shared_op->setParam(ID::A_WIDTH, max_width);
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}
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}
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typedef struct {
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RTLIL::Cell *mux;
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std::vector<OpMuxConn> ports;
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ExtSigSpec shared_operand;
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} merged_op_t;
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void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand, const SigMap &sigmap)
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{
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auto it = ports.begin();
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ExtSigSpec seed;
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while (it != ports.end()) {
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auto p = *it;
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auto op = p->op;
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TwineRef muxed_port_name = TW::A;
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if (decode_port(op, TW::A, sigmap) == shared_operand) {
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muxed_port_name = TW::B;
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}
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auto operand = decode_port(op, muxed_port_name, sigmap);
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if (seed.empty())
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seed = operand;
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if (operand.is_signed != seed.is_signed) {
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ports.erase(it);
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} else {
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++it;
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}
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}
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}
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ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxConn *> &ports, const std::map<ExtSigSpec, std::set<RTLIL::Cell *>> &operand_to_users, const SigMap &sigmap)
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{
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std::set<RTLIL::Cell *> ops_using_operand;
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std::set<RTLIL::Cell *> ops_set;
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for(const auto& p: ports)
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ops_set.insert(p->op);
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ExtSigSpec oper;
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auto op_a = seed->op;
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for (TwineRef port_name : {TW::A, TW::B}) {
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oper = decode_port(op_a, port_name, sigmap);
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auto operand_users = operand_to_users.at(oper);
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if (operand_users.size() == 1)
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continue;
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ops_using_operand.clear();
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for (auto mux_ops: ops_set)
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if (operand_users.count(mux_ops))
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ops_using_operand.insert(mux_ops);
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if (ops_using_operand.size() > 1) {
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ports.erase(std::remove_if(ports.begin(), ports.end(), [&](const OpMuxConn *p) { return !ops_using_operand.count(p->op); }),
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ports.end());
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return oper;
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}
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}
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return ExtSigSpec();
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}
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struct OptSharePass : public Pass {
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OptSharePass() : Pass("opt_share", "merge mutually exclusive cells of the same type that share an input signal") {}
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_share [selection]\n");
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log("\n");
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log("This pass identifies mutually exclusive cells of the same type that:\n");
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log(" (a) share an input signal,\n");
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log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell,\n");
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log("\n");
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log("allowing the cell to be merged and the multiplexer to be moved from\n");
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log("multiplexing its output to multiplexing the non-shared input signals.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_SHARE pass.\n");
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extra_args(args, 1, design);
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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dict<RTLIL::SigBit, int> bit_users;
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for (auto cell : module->cells()) {
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if (cell->type.in(TW($input_port), TW($output_port), TW($public)))
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continue;
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for (auto conn : cell->connections())
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for (auto bit : conn.second)
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bit_users[sigmap(bit)]++;
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}
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for (auto wire : module->wires())
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if (wire->port_id != 0)
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for (auto bit : SigSpec(wire))
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bit_users[sigmap(bit)]++;
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std::map<ExtSigSpec, std::set<RTLIL::Cell *>> operand_to_users;
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dict<RTLIL::SigBit, std::pair<RTLIL::Cell *, int>> op_outbit_to_outsig;
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bool any_shared_operands = false;
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for (auto cell : module->selected_cells()) {
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if (!cell_supported(cell))
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continue;
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bool skip = false;
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if (cell->type == TW($alu)) {
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for (TwineRef port_name : {TW::X, TW::CO}) {
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for (auto outbit : sigmap(cell->getPort(port_name)))
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if (bit_users[outbit] > 1)
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skip = true;
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}
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}
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if (skip)
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continue;
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auto mux_insig = sigmap(cell->getPort(TW::Y));
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for (int i = 0; i < GetSize(mux_insig); i++)
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op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i);
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for (TwineRef port_name : {TW::A, TW::B}) {
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auto op_insig = decode_port(cell, port_name, sigmap);
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operand_to_users[op_insig].insert(cell);
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if (operand_to_users[op_insig].size() > 1)
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any_shared_operands = true;
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}
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}
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if (!any_shared_operands)
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continue;
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// Operator outputs need to be exclusively connected to the $mux inputs in order to be mergeable. Hence we count to
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// how many points are operator output bits connected.
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std::vector<merged_op_t> merged_ops;
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for (auto mux : module->selected_cells()) {
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if (!mux->type.in(TW($mux), TW($_MUX_), TW($pmux)))
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continue;
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int mux_port_size = GetSize(mux->getPort(TW::A));
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int mux_port_num = GetSize(mux->getPort(TW::S)) + 1;
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RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(TW::B), mux->getPort(TW::A)});
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std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);
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int found = 0;
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for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {
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SigSpec mux_insig;
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if (mux_port_id == mux_port_num - 1) {
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mux_insig = sigmap(mux->getPort(TW::A));
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} else {
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mux_insig = sigmap(mux->getPort(TW::B).extract(mux_port_id * mux_port_size, mux_port_size));
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}
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for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {
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if (!op_outbit_to_outsig.count(mux_insig[mux_port_offset]))
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continue;
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RTLIL::Cell *cell;
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int op_outsig_offset;
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std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]);
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SigSpec op_outsig = sigmap(cell->getPort(TW::Y));
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int op_outsig_size = GetSize(op_outsig);
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int op_conn_width = 0;
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while (mux_port_offset + op_conn_width < mux_port_size &&
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op_outsig_offset + op_conn_width < op_outsig_size &&
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mux_insig[mux_port_offset + op_conn_width] == op_outsig[op_outsig_offset + op_conn_width])
|
|
op_conn_width++;
|
|
|
|
log_assert(op_conn_width >= 1);
|
|
|
|
bool skip = false;
|
|
for (int i = 0; i < op_outsig_size; i++) {
|
|
int expected = 1;
|
|
if (i >= op_outsig_offset && i < op_outsig_offset + op_conn_width)
|
|
expected = 2;
|
|
if (bit_users[op_outsig[i]] != expected)
|
|
skip = true;
|
|
}
|
|
if (skip) {
|
|
mux_port_offset += op_conn_width;
|
|
mux_port_offset--;
|
|
continue;
|
|
}
|
|
|
|
OpMuxConn inp = {
|
|
op_outsig.extract(op_outsig_offset, op_conn_width),
|
|
mux,
|
|
cell,
|
|
mux_port_id,
|
|
mux_port_offset,
|
|
op_outsig_offset,
|
|
};
|
|
|
|
mux_port_conns[mux_port_id].insert(inp);
|
|
|
|
mux_port_offset += op_conn_width;
|
|
mux_port_offset--;
|
|
|
|
found++;
|
|
}
|
|
}
|
|
|
|
if (found < 2)
|
|
continue;
|
|
|
|
const OpMuxConn *seed = NULL;
|
|
|
|
// Look through the bits of the $mux inputs and see which of them are connected to the operator
|
|
// results. Operator results can be concatenated with other signals before led to the $mux.
|
|
while (true) {
|
|
|
|
// Remove either the merged ports from the last iteration or the seed that failed to yield a merger
|
|
if (seed != NULL) {
|
|
mux_port_conns[seed->mux_port_id].erase(*seed);
|
|
seed = NULL;
|
|
}
|
|
|
|
// For a new merger, find the seed op connection that starts at lowest port offset among port connections
|
|
for (auto &port_conns : mux_port_conns) {
|
|
if (!port_conns.size())
|
|
continue;
|
|
|
|
const OpMuxConn *next_p = &(*port_conns.begin());
|
|
|
|
if ((seed == NULL) || (seed->mux_port_offset > next_p->mux_port_offset))
|
|
seed = next_p;
|
|
}
|
|
|
|
// Cannot find the seed -> nothing to do for this $mux anymore
|
|
if (seed == NULL)
|
|
break;
|
|
|
|
// Find all other op connections that start from the same port offset, and whose ops can be merged with the seed op
|
|
std::vector<const OpMuxConn *> mergeable_conns;
|
|
for (auto &port_conns : mux_port_conns) {
|
|
if (!port_conns.size())
|
|
continue;
|
|
|
|
const OpMuxConn *next_p = &(*port_conns.begin());
|
|
|
|
if ((next_p->op_outsig_offset == seed->op_outsig_offset) &&
|
|
(next_p->mux_port_offset == seed->mux_port_offset) && mergeable(next_p->op, seed->op) &&
|
|
next_p->sig.size() == seed->sig.size())
|
|
mergeable_conns.push_back(next_p);
|
|
}
|
|
|
|
// We need at least two mergeable connections for the merger
|
|
if (mergeable_conns.size() < 2)
|
|
continue;
|
|
|
|
// Filter mergeable connections whose ops share an operand with seed connection's op
|
|
auto shared_operand = find_shared_operand(seed, mergeable_conns, operand_to_users, sigmap);
|
|
|
|
if (shared_operand.empty())
|
|
continue;
|
|
|
|
check_muxed_operands(mergeable_conns, shared_operand, sigmap);
|
|
|
|
if (mergeable_conns.size() < 2)
|
|
continue;
|
|
|
|
// Remember the combination for the merger
|
|
std::vector<OpMuxConn> merged_ports;
|
|
for (auto p : mergeable_conns) {
|
|
merged_ports.push_back(*p);
|
|
mux_port_conns[p->mux_port_id].erase(*p);
|
|
}
|
|
|
|
seed = NULL;
|
|
|
|
merged_ops.push_back(merged_op_t{mux, merged_ports, shared_operand});
|
|
|
|
design->scratchpad_set_bool("opt.did_something", true);
|
|
}
|
|
|
|
}
|
|
|
|
for (auto &shared : merged_ops) {
|
|
log(" Found cells that share an operand and can be merged by moving the %s %s in front "
|
|
"of "
|
|
"them:\n",
|
|
shared.mux->type.unescape(), shared.mux);
|
|
for (const auto& op : shared.ports)
|
|
log(" %s\n", op.op);
|
|
log("\n");
|
|
|
|
merge_operators(module, shared.mux, shared.ports, shared.shared_operand, sigmap);
|
|
}
|
|
}
|
|
}
|
|
|
|
} OptSharePass;
|
|
|
|
PRIVATE_NAMESPACE_END
|