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This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
29 lines
421 B
Text
29 lines
421 B
Text
read_verilog -nomem2reg port_sign_extend.v
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hierarchy
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flatten
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proc
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memory
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog -nomem2reg port_sign_extend.v
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flatten
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proc
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memory
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog -nomem2reg port_sign_extend.v
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hierarchy
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proc
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memory
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equiv_make ref act equiv
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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