mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
12 lines
163 B
Text
12 lines
163 B
Text
read_verilog << EOT
|
|
|
|
module test (A, B, C, D, Y);
|
|
input A, B, C, D;
|
|
output Y;
|
|
assign Y = A^B^C^D^A;
|
|
endmodule
|
|
|
|
EOT
|
|
|
|
techmap
|
|
equiv_opt -assert extract_reduce
|