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58 lines
1.2 KiB
Text
58 lines
1.2 KiB
Text
# 5279 issue
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# Check only for complimentary patterns elimination
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read_rtlil opt_dff-simplify.il
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select -assert-count 0 t:$adffe
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select -assert-count 1 t:$adff
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select -assert-count 0 t:$ne
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opt_dff
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select -assert-count 1 t:$adffe
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select -assert-count 0 t:$adff
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select -assert-count 8 t:$ne r:A_WIDTH=3 %i
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select -assert-count 5 t:$ne r:A_WIDTH=2 %i
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select -assert-none t:$ne r:A_WIDTH=13 %i
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select -assert-none t:$ne r:A_WIDTH=14 %i
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select -assert-none t:$ne r:A_WIDTH=15 %i
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select -assert-none t:$ne r:A_WIDTH=10 %i
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select -assert-none t:$ne r:A_WIDTH=12 %i
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select -assert-none t:$ne r:A_WIDTH=11 %i
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# Check for both complimentary and redundancy elimination
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read_verilog << EOT
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module test(input clk, input h, input i, input m, output reg p);
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wire D;
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wire a;
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wire j;
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wire c;
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wire mux_test;
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wire n;
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always @(posedge clk)
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p <= D;
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assign j = n ? 1'hx : a;
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assign a = i ? mux_test : p;
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assign D = m ? h : j;
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assign c = n ? 1'hx : p;
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assign mux_test = m ? 1'hx : c;
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endmodule
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EOT
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cd test
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proc
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select -assert-count 0 t:$dffe
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select -assert-count 1 t:$dff
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select -assert-count 0 t:$ne
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opt_dff
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select -assert-count 1 t:$dffe
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select -assert-count 0 t:$dff
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select -assert-count 1 t:$ne r:A_WIDTH=2 %i
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select -assert-none t:$ne r:A_WIDTH=3 %i
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