mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
16 lines
299 B
Verilog
16 lines
299 B
Verilog
(* techmap_celltype = "$dff" *)
|
|
module dff2ff (CLK, D, Q);
|
|
parameter WIDTH = 1;
|
|
parameter CLK_POLARITY = 1;
|
|
|
|
input CLK;
|
|
(* force_downto *)
|
|
input [WIDTH-1:0] D;
|
|
(* force_downto *)
|
|
output reg [WIDTH-1:0] Q;
|
|
|
|
wire [1023:0] _TECHMAP_DO_ = "proc;;";
|
|
|
|
always @($global_clock)
|
|
Q <= D;
|
|
endmodule
|