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27 lines
923 B
Verilog
27 lines
923 B
Verilog
`ifdef DFF
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(* techmap_celltype = "$_DFF_[PN]_" *)
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module $_DFF_x_(input C, D, output Q);
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parameter [0:0] _TECHMAP_WIREINIT_Q_ = 1'bx;
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parameter _TECHMAP_CELLTYPE_ = "";
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wire D_;
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generate if (_TECHMAP_CELLTYPE_ == "$_DFF_N_") begin
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if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
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$__DFF_N__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
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$_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
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end
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else
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(* abc9_keep *) $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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end
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else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
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if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
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$__DFF_P__$abc9_flop _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q), .n1(D_));
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$_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
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end
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else
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(* abc9_keep *) $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
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end
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else if (_TECHMAP_CELLTYPE_ != "")
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$error("Unrecognised _TECHMAP_CELLTYPE_");
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endgenerate
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endmodule
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`endif
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