mirror of
https://github.com/YosysHQ/yosys
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104 lines
3.6 KiB
C++
104 lines
3.6 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "passes/opt/opt_clean/opt_clean.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool is_signed(RTLIL::Cell* cell) {
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return cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
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}
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bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
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RTLIL::SigSpec a = cell->getPort(ID::A);
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RTLIL::SigSpec y = cell->getPort(ID::Y);
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a.extend_u0(GetSize(y), is_signed(cell));
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if (a.has_const(State::Sz)) {
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RTLIL::SigSpec new_a;
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RTLIL::SigSpec new_y;
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for (int i = 0; i < GetSize(a); ++i) {
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RTLIL::SigBit b = a[i];
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if (b == State::Sz)
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return false;
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new_a.append(b);
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new_y.append(y[i]);
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}
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a = std::move(new_a);
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y = std::move(new_y);
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}
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if (!y.empty())
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new_connections.insert(ctx, {y, a});
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return true;
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}
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bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose) {
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bool did_something = false;
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for (RTLIL::Cell *cell : cells) {
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if (verbose) {
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if (cell->type == ID($connect))
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log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
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log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
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else if (cell->type == ID($input_port))
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log_debug(" removing input port marker cell `%s': %s\n", cell->name,
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log_signal(cell->getPort(ID::Y)));
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else
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log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
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log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
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}
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mod->remove(cell);
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did_something = true;
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}
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return did_something;
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}
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PRIVATE_NAMESPACE_END
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YOSYS_NAMESPACE_BEGIN
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void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::Subpool &subpool, bool verbose)
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{
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ShardedVector<RTLIL::Cell*> delcells(subpool);
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ShardedVector<RTLIL::SigSig> new_connections(subpool);
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const RTLIL::Module *const_module = module;
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subpool.run([const_module, &delcells, &new_connections](const ParallelDispatchThreadPool::RunCtx &ctx) {
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for (int i : ctx.item_range(const_module->cells_size())) {
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RTLIL::Cell *cell = const_module->cell_at(i);
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if (cell->type.in(ID($pos), ID($_BUF_), ID($buf)) && !cell->has_keep_attr()) {
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if (trim_buf(cell, new_connections, ctx))
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delcells.insert(ctx, cell);
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} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
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RTLIL::SigSpec a = cell->getPort(ID::A);
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RTLIL::SigSpec b = cell->getPort(ID::B);
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if (a.has_const() && !b.has_const())
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std::swap(a, b);
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new_connections.insert(ctx, {a, b});
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delcells.insert(ctx, cell);
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} else if (cell->type.in(ID($input_port)) && !cell->has_keep_attr()) {
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delcells.insert(ctx, cell);
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}
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}
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});
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for (RTLIL::SigSig &connection : new_connections) {
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module->connect(connection);
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}
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if (remove(delcells, module, verbose))
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module->design->scratchpad_set_bool("opt.did_something", true);
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}
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YOSYS_NAMESPACE_END
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