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$__QLF_TDP36K_MERGED exists only as a techmap template, so nothing in the design describes its interface and Cell::port_dir() has nothing to answer with. On a normalized design an unknown direction reads as "output", so every input got a fresh driven wire and a $connect tying it back to its source -- and the constant bits of an address, having no source to tie back to, were dropped and folded to x by the next `opt -undriven`. That silently turned every TDP36K address, byte-enable and read-enable constant into x, and qlf_k6n10f/t_mem1 failed its simulation assertion. Declare each port on a generated blackbox first, the way memory_libmap already does for the cells it instantiates. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01MQU5XCqDYY8MbivGkNRrDo |
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| achronix | ||
| analogdevices | ||
| anlogic | ||
| common | ||
| coolrunner2 | ||
| easic | ||
| efinix | ||
| fabulous | ||
| gatemate | ||
| gowin | ||
| greenpak4 | ||
| ice40 | ||
| intel | ||
| intel_alm | ||
| lattice | ||
| microchip | ||
| nanoxplore | ||
| quicklogic | ||
| sf2 | ||
| xilinx | ||
| CMakeLists.txt | ||
| fix_mod.py | ||