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5e641acc90
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
117 lines
2.1 KiB
Verilog
117 lines
2.1 KiB
Verilog
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// test_parse2synthtrans_behavopt_1_test.v
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module f1_test(in, out, clk, reset);
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input in, reset;
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output reg out;
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input clk;
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reg signed [3:0] a;
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reg signed [3:0] b;
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reg signed [3:0] c;
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reg [5:0] d;
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reg [5:0] e;
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always @(clk or reset) begin
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a = -4;
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b = 2;
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c = a + b;
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d = a + b + c;
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d = d*d;
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if(b)
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e = d*d;
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else
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e = d + d;
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end
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endmodule
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// test_parse2synthtrans_case_1_test.v
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module f2_demultiplexer1_to_4 (out0, out1, out2, out3, in, s1, s0);
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output out0, out1, out2, out3;
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reg out0, out1, out2, out3;
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input in;
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input s1, s0;
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reg [3:0] encoding;
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reg [1:0] state;
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always @(encoding) begin
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case (encoding)
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4'bxx11: state = 1;
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4'bx0xx: state = 3;
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4'b11xx: state = 4;
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4'bx1xx: state = 2;
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4'bxx1x: state = 1;
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4'bxxx1: state = 0;
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default: state = 0;
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endcase
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end
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always @(encoding) begin
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case (encoding)
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4'b0000: state = 1;
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default: state = 0;
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endcase
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end
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endmodule
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// test_parse2synthtrans_contassign_1_test.v
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module f3_test(in, out);
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input wire in;
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output out;
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assign out = (in+in);
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assign out = 74;
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endmodule
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// test_parse2synthtrans_module_basic0_test.v
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module f4_test;
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endmodule
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// test_parse2synthtrans_operators_1_test.v
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module f5_test(in, out);
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input in;
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output out;
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parameter p1 = 10;
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parameter p2 = 5;
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assign out = +p1;
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assign out = -p2;
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assign out = p1 + p2;
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assign out = p1 - p2;
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endmodule
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// test_parse2synthtrans_param_1_test.v
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module f6_test(in, out);
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input in;
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output out;
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parameter p = 10;
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assign out = p;
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endmodule
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// test_parse2synthtrans_port_scalar_1_test.v
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module f7_test(in, out, io);
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inout io;
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output out;
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input in;
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endmodule
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// test_parse2synthtrans_port_vector_1_test.v
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module f8_test(in1, in2, out1, out2, io1, io2);
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inout [1:0] io1;
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inout [0:1] io2;
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output [1:0] out1;
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output [0:1] out2;
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input [1:0] in1;
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input [0:1] in2;
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endmodule
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// test_parse2synthtrans_v2k_comb_logic_sens_list_test.v
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module f9_test(q, d, clk, reset);
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output reg q;
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input d, clk, reset;
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always @ (posedge clk, negedge reset)
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if(!reset) q <= 0;
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else q <= d;
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endmodule
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