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4ffdee65e0
statics were obviously wrong -- may be multiple instantiations of any given module. Extend test to cover this.
9 lines
144 B
Verilog
9 lines
144 B
Verilog
module tb;
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reg clk = 0;
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top uut1 (.clk(clk));
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top uut2 (.clk(clk));
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always #1 clk <= ~clk;
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initial #20 $finish;
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endmodule
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