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https://github.com/YosysHQ/yosys
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121 lines
2 KiB
Text
121 lines
2 KiB
Text
design -reset
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read_verilog <<EOT
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module foo (CLK, Q, QQQ);
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input CLK;
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output reg QQQ;
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output reg Q = 1'b1;
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assign QQQ = Q;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init %i
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abstract -init w:QQQ
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check -assert
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select -assert-count 0 w:Q a:init %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q, QQQ);
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input CLK;
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output reg QQQ;
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output reg [1:0] Q = 1'b1;
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assign QQQ = Q;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init w:QQQ
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// downto
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output reg [1:0] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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design -save basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -load basic
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0:1 w:Q
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check -assert
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select -assert-count 0 w:Q a:init %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// downto
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output reg [1:0] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -rtlilslice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// upto
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output reg [0:1] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -slice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'bx1 %i
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design -reset
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read_verilog <<EOT
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module foo (CLK, Q);
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input CLK;
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// upto
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output reg [0:1] Q = 1'b1;
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always @(posedge CLK)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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select -assert-count 1 w:Q a:init=2'b01 %i
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abstract -init -rtlilslice 0 w:Q
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check -assert
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select -assert-count 1 w:Q a:init=2'b0x %i
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