mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-15 08:56:41 +00:00
41 lines
1.5 KiB
Text
41 lines
1.5 KiB
Text
# ================================ ROM ================================
|
|
# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
|
|
|
|
## With parameters
|
|
|
|
design -reset; read_verilog -defer ../common/blockrom.v
|
|
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
|
hierarchy -top sync_rom
|
|
synth_ice40 -top sync_rom; cd sync_rom
|
|
select -assert-count 0 t:SB_RAM40_4K # too inefficient
|
|
select -assert-min 1 t:SB_LUT4
|
|
|
|
design -reset; read_verilog -defer ../common/blockrom.v
|
|
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
|
hierarchy -top sync_rom
|
|
setattr -set syn_romstyle "ebr" m:memory
|
|
synth_ice40 -top sync_rom; cd sync_rom
|
|
select -assert-count 1 t:SB_RAM40_4K
|
|
|
|
design -reset; read_verilog -defer ../common/blockrom.v
|
|
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
|
hierarchy -top sync_rom
|
|
setattr -set rom_block 1 m:memory
|
|
synth_ice40 -top sync_rom; cd sync_rom
|
|
select -assert-count 1 t:SB_RAM40_4K
|
|
|
|
design -reset; read_verilog -defer ../common/blockrom.v
|
|
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
|
hierarchy -top sync_rom
|
|
setattr -set syn_romstyle "logic" m:memory
|
|
synth_ice40 -top sync_rom; cd sync_rom
|
|
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
|
|
select -assert-min 1 t:SB_LUT4
|
|
|
|
design -reset; read_verilog -defer ../common/blockrom.v
|
|
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
|
|
hierarchy -top sync_rom
|
|
setattr -set logic_block 1 m:memory
|
|
synth_ice40 -top sync_rom; cd sync_rom
|
|
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
|
|
select -assert-min 1 t:SB_LUT4
|