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48 lines
1.9 KiB
Text
48 lines
1.9 KiB
Text
# ================================ RAM ================================
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# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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## With parameters
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # too inefficient
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K # any case works
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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