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26 lines
1 KiB
Text
26 lines
1 KiB
Text
# ================================ RAM ================================
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# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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