mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 17:45:33 +00:00
237e454131
Use `Design::selected_modules()` directly, popping at the end instead of copying the selection. Also default to a complete selection so that boxes work as before. Simplify to using `RTLIL::SELECT_WHOLE_CMDERR` instead of doing it manually. Also add tests for importing selections with boxes.
29 lines
668 B
Text
29 lines
668 B
Text
read_verilog -specify boxes.v
|
|
design -save read
|
|
|
|
logger -expect-no-warnings
|
|
|
|
delete =bb %n
|
|
select -assert-mod-count 1 =*
|
|
design -stash just_bb
|
|
|
|
design -import just_bb
|
|
select -assert-mod-count 0 *
|
|
select -assert-mod-count 1 =*
|
|
design -reset
|
|
|
|
design -import just_bb -as new
|
|
select -assert-mod-count 0 *
|
|
select -assert-mod-count 1 =*
|
|
design -reset
|
|
|
|
design -import read -as new_top top
|
|
design -import read -as new_bb =bb
|
|
select -assert-mod-count 1 *
|
|
select -assert-mod-count 2 =*
|
|
|
|
logger -check-expected
|
|
|
|
logger -expect warning "Selection .wb. did not match any module\." 1
|
|
logger -expect error "No top module found in source design\." 1
|
|
design -import read -as new_wb wb
|