yosys/tests/fmt/.gitignore at emil/cell-playground-3 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-22 08:35:32 +00:00

whitequark c285880684 fmt: add tests for Verilog round trip of format expressions.

2023-08-11 04:46:52 +02:00

3 lines

25 B

Text

Raw Permalink Blame History

	`*.log`
	`iverilog-*`
	`yosys-*`