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32 lines
794 B
Text
32 lines
794 B
Text
read_verilog -icells opt_rmdff.v
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prep
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design -stash gold
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read_verilog -icells opt_rmdff.v
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proc
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opt_dff
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select -assert-count 0 c:remove*
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select -assert-min 7 c:keep*
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select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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cd gold
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# fix up the "EN is don't care" cases, so that the gold output can't
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# become defined by using the properties of an undefined enable. (Both
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# remove6 and remove15 have active-low enables.)
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connect -port remove6 EN 1'b1
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connect -port remove15 E 1'b1
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cd ..
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clk2fflogic
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opt_clean
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miter -equiv -ignore_gold_x -make_assert -make_outputs -make_outcmp -flatten gold gate miter
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hierarchy -top miter
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sat -verify -prove-asserts -enable_undef -set-init-undef -seq 10 -show-public miter
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