mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
113 lines
3.2 KiB
Text
113 lines
3.2 KiB
Text
### Always-active SRST removal.
|
|
|
|
read_verilog -icells <<EOT
|
|
|
|
module top(...);
|
|
|
|
input CLK;
|
|
input [1:0] D;
|
|
(* init=12'h555 *)
|
|
output [11:0] Q;
|
|
input SRST;
|
|
input EN;
|
|
|
|
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b1), .D(D), .Q(Q[1:0]));
|
|
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[3:2]));
|
|
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[5:4]));
|
|
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .SRST(1'bx), .D(D), .Q(Q[7:6]));
|
|
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[9:8]));
|
|
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[11:10]));
|
|
|
|
|
|
endmodule
|
|
|
|
EOT
|
|
|
|
design -save orig
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff
|
|
design -load postopt
|
|
select -assert-count 0 t:$sdff
|
|
select -assert-count 0 t:$sdffe
|
|
select -assert-count 0 t:$sdffce
|
|
select -assert-count 4 t:$dff
|
|
select -assert-count 2 t:$dffe
|
|
|
|
design -load orig
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
|
design -load postopt
|
|
select -assert-count 1 t:$sdff
|
|
select -assert-count 1 t:$sdffe
|
|
select -assert-count 1 t:$sdffce
|
|
select -assert-count 2 t:$dff
|
|
select -assert-count 1 t:$dffe
|
|
|
|
design -load orig
|
|
simplemap
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff
|
|
design -load postopt
|
|
select -assert-none t:$_SDFF_???_
|
|
select -assert-none t:$_SDFFE_????_
|
|
select -assert-none t:$_SDFFCE_????_
|
|
select -assert-count 8 t:$_DFF_?_
|
|
select -assert-count 4 t:$_DFFE_??_
|
|
|
|
design -load orig
|
|
simplemap
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff -keepdc
|
|
design -load postopt
|
|
select -assert-count 2 t:$_SDFF_???_
|
|
select -assert-count 2 t:$_SDFFE_????_
|
|
select -assert-count 2 t:$_SDFFCE_????_
|
|
select -assert-count 4 t:$_DFF_?_
|
|
select -assert-count 2 t:$_DFFE_??_
|
|
|
|
design -reset
|
|
|
|
|
|
### Never-active SRST removal.
|
|
|
|
read_verilog -icells <<EOT
|
|
|
|
module top(...);
|
|
|
|
input CLK;
|
|
input [1:0] D;
|
|
output [5:0] Q;
|
|
input SRST;
|
|
input EN;
|
|
|
|
$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b0), .D(D), .Q(Q[1:0]));
|
|
$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
|
|
$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[5:4]));
|
|
|
|
endmodule
|
|
|
|
EOT
|
|
|
|
design -save orig
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff
|
|
design -load postopt
|
|
select -assert-none t:$sdff
|
|
select -assert-none t:$sdffe
|
|
select -assert-none t:$sdffce
|
|
select -assert-count 1 t:$dff
|
|
select -assert-count 2 t:$dffe
|
|
|
|
design -load orig
|
|
simplemap
|
|
|
|
equiv_opt -undef -assert -multiclock opt_dff
|
|
design -load postopt
|
|
select -assert-none t:$_SDFF_???_
|
|
select -assert-none t:$_SDFFE_????_
|
|
select -assert-none t:$_SDFFCE_????_
|
|
select -assert-count 2 t:$_DFF_P_
|
|
select -assert-count 4 t:$_DFFE_PP_
|
|
|
|
design -reset
|
|
|