mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 00:26:40 +00:00
4 lines
83 B
Verilog
4 lines
83 B
Verilog
module test(A, B, Y);
|
|
input [1:0] A, B;
|
|
output [1:0] Y = A * B;
|
|
endmodule
|