mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-23 17:15:33 +00:00
3 lines
66 B
Verilog
3 lines
66 B
Verilog
module test(input a, output x, y);
|
|
assign x = a, y = a;
|
|
endmodule
|