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43 lines
924 B
Text
43 lines
924 B
Text
read_verilog <<EOT
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module delay #(parameter width=2, taps=1)(
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input clk,
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input [width-1:0] d_in,
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output reg [width-1:0] d_out
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);
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generate
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genvar k;
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reg [width-1:0] mem[0:taps-1];
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for (k=0;k<taps;k=k+1) begin : delay_gen
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always @(posedge clk) begin
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//if (k == 0)
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// mem[k] = d_in;
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//else
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// mem[k] = mem[k-1];
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mem[k] <= k==0 ? d_in : mem[k-1]; // <<<<<<<<< ERROR IS HERE
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end
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end
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endgenerate
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always @(posedge clk) begin
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b <= mem[taps-1];
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end
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endmodule
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module top (input clk, input wire [3:0] a, output wire [3:0] b);
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delay #(.width(4), .taps(1)) d(clk, a, b);
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endmodule
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EOT
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design -reset
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read_verilog <<EOT
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module top(output o1, o2);
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wire i [0:0]; // Only errors out on unpacked...
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assign o1 = (0 == 0) ? i[0] : i[-1];
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assign o2 = (1 > 1) ? i[1] : i[0];
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endmodule
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EOT
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