mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-22 08:35:32 +00:00
6 lines
149 B
Text
6 lines
149 B
Text
logger -werror "is implicitly declared." -expect error "is implicitly declared." 1
|
|
read_verilog << EOF
|
|
module top(...);
|
|
assign b = w;
|
|
endmodule
|
|
EOF
|