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yosys/passes
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Benjamin Barzen 8611429237
ABC9: Cell Port Bug Patch (#3670) 
* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
2023-04-22 16:24:36 -07:00
..
cmds stat: pass down quiet arg 2023-02-28 17:12:55 +01:00
equiv Merge pull request #3126 from georgerennie/equiv_make_assertions 2023-02-14 17:15:55 +01:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
opt Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
pmgen Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
proc Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
sat sim: For yw cosim, drive parent module's signals for input ports 2023-02-13 12:26:06 +01:00
techmap ABC9: Cell Port Bug Patch (#3670) 2023-04-22 16:24:36 -07:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00