mirror of
https://github.com/YosysHQ/yosys
synced 2026-05-25 19:36:21 +00:00
28 lines
337 B
CMake
28 lines
337 B
CMake
yosys_pass(synth_achronix
|
|
synth_achronix.cc
|
|
REQUIRES
|
|
abc
|
|
blackbox
|
|
check
|
|
clean
|
|
deminout
|
|
dfflegalize
|
|
flatten
|
|
hierarchy
|
|
iopadmap
|
|
memory_map
|
|
opt
|
|
proc
|
|
read_verilog
|
|
setundef
|
|
stat
|
|
synth
|
|
techmap
|
|
tribuf
|
|
write_verilog
|
|
DATA_DIR
|
|
achronix
|
|
DATA_FILES
|
|
speedster22i/cells_sim.v
|
|
speedster22i/cells_map.v
|
|
)
|