/* Liberty 2007: example 2-4          */
/* Direction of pins in bundle groups */
library(bundle_example) {
  technology (cmos);
  revision : 1.0;
  
  time_unit                     : "1ps";
  pulling_resistance_unit       : "1kohm";  
  voltage_unit                  : "1V";
  current_unit                  : "1uA";  
  
  capacitive_load_unit(1,ff);
  
  default_inout_pin_cap         :  7.0;
  default_input_pin_cap         :  7.0;
  default_output_pin_cap        :  0.0;
  default_fanout_load           :  1.0;

  default_wire_load_capacitance : 0.1;
  default_wire_load_resistance  : 1.0e-3;
  default_wire_load_area        : 0.0;

  nom_process                   :  1.0;
  nom_temperature               : 25.0;
  nom_voltage                   :  1.2;
  
  delay_model                   : generic_cmos;
  
  cell (inv) {
    area : 16;
    cell_leakage_power : 8;
    bundle (Z) {
      members (Z0, Z1, Z2, Z3);
      direction : output;
      function : "D";
      pin (Z0) {
        direction : output;
        timing () {
          intrinsic_rise : 0.4;
          intrinsic_fall : 0.4;
          related_pin : "D0";
        }
      }
      pin (Z1) {
        direction : output;
        timing () {
          intrinsic_rise : 0.4;
          intrinsic_fall : 0.4;
          related_pin : "D1";
        }
      }
    }
    bundle (D) {
      members (D0, D1, D2, D3);
      direction : input;
      capacitance : 1;
      pin (D0) {
        direction : input;
      }
    }
  }
}