read_verilog squarediffmult.v
hierarchy -top squarediffmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd squarediffmult
stat
#Vivado synthesizes 16 FDRE, 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 117 t:FDRE
select -assert-count 223 t:LUT2
select -assert-count 50 t:LUT3
select -assert-count 38 t:LUT4
select -assert-count 56 t:LUT5
select -assert-count 372 t:LUT6
select -assert-count 49 t:MUXCY
select -assert-count 99 t:MUXF7
select -assert-count 26 t:MUXF8
select -assert-count 51 t:XORCY

select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D