read_verilog dynpreaddmultadd.v
hierarchy -top dynpreaddmultadd
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd dynpreaddmultadd

#Vivado synthesizes 1 DSP48E1.
select -assert-count 1 t:BUFG
select -assert-count 75 t:FDRE
select -assert-count 8 t:LUT1
select -assert-count 131 t:LUT2
select -assert-count 19 t:LUT3
select -assert-count 26 t:LUT4
select -assert-count 12 t:LUT5
select -assert-count 142 t:LUT6
select -assert-count 48 t:MUXCY
select -assert-count 50 t:MUXF7
select -assert-count 15 t:MUXF8
select -assert-count 52 t:XORCY

select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D