read_verilog cmult.v
hierarchy -top cmult
proc
memory -nomap
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
memory
opt -full

# TODO
#equiv_opt -run prove: -assert null
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter

design -load postopt
cd cmult
#Vivado synthesizes 3 DSP48E1, 68 FDRE.
select -assert-count 1 t:BUFG
select -assert-count 281 t:FDRE
select -assert-count 18 t:LUT1
select -assert-count 467 t:LUT2
select -assert-count 187 t:LUT3
select -assert-count 98 t:LUT4
select -assert-count 165 t:LUT5
select -assert-count 1596 t:LUT6
select -assert-count 222 t:MUXCY
select -assert-count 393 t:MUXF7
select -assert-count 121 t:MUXF8
select -assert-count 85 t:SRL16E
select -assert-count 230 t:XORCY

select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:SRL16E t:XORCY %% t:* %D