#include "kernel/unstable/patch.h"
#include "kernel/celltypes.h"
#include "kernel/rtlil.h"

YOSYS_NAMESPACE_BEGIN

/** 
* Notes
*
* If we want GC, we need more indices
* namely user count (and users?). This should be optional
*
*
*/
using namespace RTLIL;

template class CellAdderMixin<Patch>;

Cell* Patch::addCell(IdString name, IdString type) {
	cells_.emplace(cells_.end(), std::make_unique<Cell>(Cell::ConstructToken{}));

	Cell* cell = cells_.back().get();
	cell->name = std::move(name);
	cell->type = type;
	return cell;
}

Wire* Patch::addWire(IdString name, int width) {
	(void)name;
	(void)width;
	log_assert(false);
	return nullptr;
}

void Patch::patch() {
	for (auto& cell: cells_) {
		Cell* new_cell = mod->addCell(cell->name, cell->type);
		for (auto [port_name, sig] : new_cell->connections()) {
			log_assert(yosys_celltypes.cell_known(cell->type));
			auto dir = cell->port_dir(port_name);
			if (dir == PD_OUTPUT || dir == PD_INOUT) {
				for (auto chunk : sig.chunks()) {
					log_assert(chunk.is_wire());
					auto* wire = chunk.wire;
					// Unwire old driver
					wire->driverCell_->setPort(wire->driverPort_, SigSpec());
					// Maintain bufnorm
					wire->driverCell_ = new_cell;
					wire->driverPort_ = port_name;
				}
			}
		}
	}
}


YOSYS_NAMESPACE_END