yosys_pass(synth_gowin
	synth_gowin.cc
	REQUIRES
		abc
		abc9
		alumacc
		autoname
		blackbox
		check
		clean
		deminout
		dfflegalize
		flatten
		fsm
		hierarchy
		hilomap
		iopadmap
		memory
		memory_libmap
		memory_map
		opt
		opt_clean
		opt_expr
		opt_lut_ins
		peepopt
		proc
		read_verilog
		setundef
		share
		simplemap
		sort
		splitnets
		stat
		techmap
		tribuf
		wreduce
		write_json
		write_verilog
	DATA_DIR
		gowin
	DATA_FILES
		cells_map.v
		cells_sim.v
		cells_latch.v
		cells_xtra_gw1n.v
		cells_xtra_gw2a.v
		cells_xtra_gw5a.v
		arith_map.v
		brams_map.v
		brams_map_gw5a.v
		brams.txt
		lutrams_map.v
		lutrams.txt
		dsp_map.v
)