read_verilog latches.v
design -save read

proc
hierarchy -top latchp
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchp # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4

select -assert-none t:EFX_LUT4 %% t:* %D


design -load read
proc
hierarchy -top latchn
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchn # Constrain all select calls below inside the top module
select -assert-count 1 t:EFX_LUT4

select -assert-none t:EFX_LUT4 %% t:* %D


design -load read
proc
hierarchy -top latchsr
# Can't run any sort of equivalence check because latches are blown to LUTs
synth_efinix
cd latchsr # Constrain all select calls below inside the top module
select -assert-count 2 t:EFX_LUT4

select -assert-none t:EFX_LUT4 %% t:* %D