read_rtlil << EOT

module \top
	wire width 4 input 0 \A
	wire width 4 input 1 \C
	wire width 2 input 2 \S
	wire width 4 output 3 \Y

	cell $pmux $0
		parameter \WIDTH 4
		parameter \S_WIDTH 2
		connect \A \A
		connect \B { \C \A }
		connect \S \S
		connect \Y \Y
	end
end

EOT

equiv_opt -assert opt_reduce
opt_reduce
select -assert-count 0 t:$pmux
select -assert-count 1 t:$mux

design -reset

read_rtlil << EOT

module \top
	wire width 4 input 0 \A
	wire width 2 input 1 \S
	wire width 4 output 2 \Y

	cell $pmux $0
		parameter \WIDTH 4
		parameter \S_WIDTH 2
		connect \A \A
		connect \B { \A \A }
		connect \S \S
		connect \Y \Y
	end
end

EOT

equiv_opt -assert opt_reduce
opt_reduce
select -assert-count 0 t:$pmux
select -assert-count 0 t:$mux