read_verilog < B; assign Y = A > B; endmodule EOT # Exercise the general case in hash_cell_inputs - accept opt_expr select -assert-count 2 t:$gt equiv_opt -assert opt_merge design -load postopt select -assert-count 1 t:$gt design -reset read_verilog < B; assign Y = A > C; // <- look here endmodule EOT # Exercise the general case in hash_cell_inputs - reject opt_expr select -assert-count 2 t:$gt opt_merge select -assert-count 2 t:$gt