read_verilog mux.v
proc
flatten
equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module

select -assert-count 1  t:AL_MAP_LUT3
select -assert-count 4  t:AL_MAP_LUT4
select -assert-count 4  t:AL_MAP_LUT5
select -assert-count 1  t:AL_MAP_LUT6
select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D