read_verilog adffs.v
proc
async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock
flatten
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 1 t:DFF
select -assert-count 1 t:DFFN
select -assert-count 2 t:DFFSR
select -assert-count 7 t:LUT4
select -assert-none t:DFF t:DFFN t:DFFSR t:LUT4 %% t:* %D