read_verilog ../common/fsm.v
hierarchy -top fsm
proc
flatten

equiv_opt -run :prove -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v
async2sync
miter -equiv -make_assert -flatten gold gate miter
stat
sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter

design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd fsm # Constrain all select calls below inside the top module

select -assert-count 6 t:LUTFF
select -assert-max 5 t:LUT2
select -assert-max 4 t:LUT3
select -assert-max 8 t:LUT4
select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUTFF %% t:* %D