# ABC synthesis comparison: with vs without csa_tree

# Baseline: no csa_tree
read_verilog abc_bench_add8.v
hierarchy -top abc_bench_add8
proc; opt
techmap
abc -g AND,OR,XOR
opt_clean
stat

# Baseline is typically 238 gates — assert it's above 235
select -assert-min 236 t:$_AND_ t:$_OR_ t:$_XOR_ %u

design -reset

# With csa_tree
read_verilog abc_bench_add8.v
hierarchy -top abc_bench_add8
proc; opt
csa_tree
techmap
abc -g AND,OR,XOR
opt_clean
stat

# CSA was giving ~232 gates, assert rough equality
select -assert-max 235 t:$_AND_ t:$_OR_ t:$_XOR_ %u

design -reset

# Depth-optimal: baseline
read_verilog abc_bench_add8.v
hierarchy -top abc_bench_add8
proc; opt
techmap
abc -D 1
opt_clean
stat

# Baseline depth-optimal is  ~243 cells
select -assert-min 240 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u

design -reset

# Depth-optimal: with csa_tree
read_verilog abc_bench_add8.v
hierarchy -top abc_bench_add8
proc; opt
csa_tree
techmap
abc -D 1
opt_clean
stat

# CSA depth-optimal is ~232 cells, must be under baseline
select -assert-max 236 t:$_AND_ t:$_NAND_ t:$_OR_ t:$_NOR_ t:$_XOR_ t:$_XNOR_ t:$_NOT_ %u

log "CSA depth and gate count: ok"