read_verilog sub_mixed.v
hierarchy -top sub_mixed
proc; opt_clean
csa_tree
opt_clean

# 10 + 20 - 5 + 3 = 28
sat -set a 10 -set b 20 -set c 5 -set d 3 -prove y 28

# 0 + 0 - 0 + 0 = 0
sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0

# 100 + 50 - 30 + 10 = 130
sat -set a 100 -set b 50 -set c 30 -set d 10 -prove y 130

# 1 + 1 - 255 + 1 = 4
sat -set a 1 -set b 1 -set c 255 -set d 1 -prove y 4

log "sub_mixed vectors: ok"

design -reset

read_verilog sub_all.v
hierarchy -top sub_all
proc; opt_clean
csa_tree
opt_clean

# 100 - 10 - 20 - 30 = 40
sat -set a 100 -set b 10 -set c 20 -set d 30 -prove y 40

# 0 - 0 - 0 - 0 = 0
sat -set a 0 -set b 0 -set c 0 -set d 0 -prove y 0

# 255 - 1 - 1 - 1 = 252
sat -set a 255 -set b 1 -set c 1 -set d 1 -prove y 252

log "sub_all vectors: ok"