module latch (D, G, Q, QN);
  reg IQ, IQN;
  input D;
  input G;
  output Q;
  assign Q = IQ; // IQ
  output QN;
  assign QN = IQN; // IQN
  always @* begin
    if ((G)) begin
      IQ <= D;
      IQN <= ~(D);
    end
  end
endmodule