[Makefile.conf] CONFIG := clang
[  0%] Building kernel/version_2223d7848.cc
cd tests/arch/anlogic/ && bash run-test.sh
[ 38%] Building passes/hierarchy/flatten.o
cd tests/arch/ecp5/ && bash run-test.sh
cd tests/arch/efinix/ && bash run-test.sh
cd tests/arch/gatemate/ && bash run-test.sh
cd tests/arch/gowin/ && bash run-test.sh
cd tests/arch/ice40/ && bash run-test.sh
cd tests/arch/intel_alm/ && bash run-test.sh
cd tests/arch/machxo2/ && bash run-test.sh
cd tests/arch/microchip/ && bash run-test.sh
cd tests/arch/nanoxplore/ && bash run-test.sh
cd tests/arch/nexus/ && bash run-test.sh
cd tests/arch/quicklogic/pp3/ && bash run-test.sh
cd tests/arch/quicklogic/qlf_k6n10f/ && bash run-test.sh
cd tests/arch/xilinx/ && bash run-test.sh
cd tests/opt/ && bash run-test.sh
cd tests/sat/ && bash run-test.sh
cd tests/sim/ && bash run-test.sh
cd tests/svtypes/ && bash run-test.sh
cd tests/techmap/ && bash run-test.sh
cd tests/various/ && bash run-test.sh
cd tests/verilog/ && bash run-test.sh
Generate FST for sim models
Test tb_adffe
FST info: dumpfile tb_adffe.fst opened for output.
tb/tb_adffe.v:56: $finish called at 190 (1ns)
Test tb_adff
[ 38%] Building kernel/version_2223d7848.o
FST info: dumpfile tb_adff.fst opened for output.
tb/tb_adff.v:38: $finish called at 110 (1ns)
Test tb_adlatch
FST info: dumpfile tb_adlatch.fst opened for output.
tb/tb_adlatch.v:68: $finish called at 250 (1ns)
Test tb_aldffe
FST info: dumpfile tb_aldffe.fst opened for output.
tb/tb_aldffe.v:73: $finish called at 270 (1ns)
Test tb_aldff
FST info: dumpfile tb_aldff.fst opened for output.
tb/tb_aldff.v:71: $finish called at 270 (1ns)
Test tb_dffe
FST info: dumpfile tb_dffe.fst opened for output.
tb/tb_dffe.v:40: $finish called at 120 (1ns)
Test tb_dffsr
FST info: dumpfile tb_dffsr.fst opened for output.
tb/tb_dffsr.v:67: $finish called at 250 (1ns)
Test tb_dff
FST info: dumpfile tb_dff.fst opened for output.
tb/tb_dff.v:45: $finish called at 150 (1ns)
Test tb_dlatchsr
FST info: dumpfile tb_dlatchsr.fst opened for output.
tb/tb_dlatchsr.v:63: $finish called at 250 (1ns)
Test tb_dlatch
FST info: dumpfile tb_dlatch.fst opened for output.
tb/tb_dlatch.v:48: $finish called at 160 (1ns)
Test tb_sdffce
FST info: dumpfile tb_sdffce.fst opened for output.
tb/tb_sdffce.v:77: $finish called at 300 (1ns)
Test tb_sdffe
FST info: dumpfile tb_sdffe.fst opened for output.
tb/tb_sdffe.v:68: $finish called at 250 (1ns)
Test tb_sdff
FST info: dumpfile tb_sdff.fst opened for output.
tb/tb_sdff.v:46: $finish called at 150 (1ns)
[100%] Building yosys
make -C tests/arch/anlogic -f run-test.mk
make -C tests/arch/ecp5 -f run-test.mk
make -C tests/arch/efinix -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/anlogic'
make -C tests/arch/gatemate -f run-test.mk
make -C tests/arch/gowin -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/ecp5'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/efinix'
make -C tests/arch/ice40 -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/gatemate'
make -C tests/arch/intel_alm -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/gowin'
make -C tests/arch/machxo2 -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/ice40'
make -C tests/arch/microchip -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/intel_alm'
make -C tests/arch/nanoxplore -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/machxo2'
make -C tests/arch/nexus -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/microchip'
make -C tests/arch/quicklogic/pp3 -f run-test.mk
make -C tests/arch/quicklogic/qlf_k6n10f -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/nanoxplore'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/nexus'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/quicklogic/qlf_k6n10f'
make -C tests/arch/xilinx -f run-test.mk
make -C tests/opt -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/quicklogic/pp3'
make -C tests/sat -f run-test.mk
make -C tests/sim -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/opt'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/sat'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/xilinx'
make -C tests/svtypes -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/sim'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/svtypes'
make -C tests/techmap -f run-test.mk
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/techmap'
make -C tests/various -f run-test.mk
make -C tests/verilog -f run-test.mk
cd tests/memories && bash run-test.sh "" ""
cd tests/aiger && bash run-test.sh "" ""
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/various'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/verilog'
cd tests/alumacc && bash run-test.sh "" ""
cd tests/simple && bash run-test.sh ""
cd tests/simple_abc9 && bash run-test.sh ""
cd tests/hana && bash run-test.sh ""
cd tests/asicworld && bash run-test.sh ""
cd tests/share && bash run-test.sh ""
Running basic.ys..
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/memories'
Checking and_.aag.
cd tests/opt_share && bash run-test.sh ""
cd tests/fsm && bash run-test.sh ""
cd tests/memlib && bash run-test.sh ""
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/hana'
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/simple'
cd tests/bram && bash run-test.sh ""
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/asicworld'
cd tests/svinterfaces && bash run-test.sh ""
cd tests/xprop && bash run-test.sh ""
cd tests/select && bash run-test.sh ""
cd tests/peepopt && bash run-test.sh ""
cd tests/proc && bash run-test.sh ""
cd tests/blif && bash run-test.sh ""
cd tests/arch && bash run-test.sh ""
cd tests/rpc && bash run-test.sh ""
cd tests/memfile && bash run-test.sh ""
generating tests..
cd tests/fmt && bash run-test.sh ""
cd tests/cxxrtl && bash run-test.sh ""
cd tests/liberty && bash run-test.sh ""
Running boxes_equals_name.ys..
generating tests..
Running bug2729.ys..
Running bug_1268.ys..
+ awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}'
+ ../../yosys -p 'read_verilog initial_display.v'
generating tests..
Running muldiv_c.ys..
Test: svinterface1 -> Running syntax check on arch sim models
Testing on busdef.lib..
Running from the parent directory with content1.dat
+ run_subtest value
+ local subtest=value
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/simple_abc9'
Test ../../techlibs/achronix/speedster22i/cells_sim.v ->Running exec.ys..
generating tests..
 ok
Test ../../techlibs/anlogic/cells_sim.v ->xprop PRNG seed: 1272022655
 ok
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/xprop'
running tests..
Test ../../techlibs/coolrunner2/cells_sim.v ->PRNG seed: 8457212978369919983
 ok
[0]Test ../../techlibs/ecp5/cells_sim.v ->make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/memlib'
 ok
Test ../../techlibs/efinix/cells_sim.v ->PRNG seed: 779274
 ok
Test ../../techlibs/gatemate/cells_sim.v -> ok
Test ../../techlibs/gowin/cells_sim.v ->running tests..
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/fsm'
[0] ok
Warning: Literal has a width of 16 bit, but value requires 184 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 183 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 182 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 165 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 152 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 126 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 108 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 150 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 164 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 181 bit. (<<EOT:1)
Test ../../techlibs/greenpak4/cells_sim.v -> ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->running tests..
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/bram'
../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
running tests..
make[1]: Entering directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/opt_share'
[0][1][3][4][6][5] ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->[2][8][9][7][11][12][13][14][10]../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
[15][16][17][18][19][20][21][22][23][24] ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->[27][28][25][26][29]../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
[30][31][32][33][35][36][37][34][38][39][40][42][41][43][47][46][45][44]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
[48]Passed efinix-add_sub.ys
Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits.
 ok
[49][50][51]Test: t_init_lut_x_none -> ok
[52]Test: t_async_small -> ok
Test: t_sync_trans_old_old -> ok
[53][54]Test ../../techlibs/intel/cycloneiv/cells_sim.v ->[55][56]Test: t_sp_nc_nc -> ok
[57][58][59][60][61]Test: t_init_4b1B_x_none -> ok
[63][62][64][65][68][69][66][70][67] ok
[74][75][72]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
[73][76][77]Test ../../techlibs/intel/cycloneive/cells_sim.v ->[71]Test: t_clock_a4_wPOSrNEGsFalse -> ok
Test: undef_eqx_nex -> ok
[78]Test: t_clock_a4_wPOSrANYsFalse -> ok
[79]Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
[81] ok
[80][82][86][85][89][88][84][90]Test: t_sp_nc_new_only -> ok
Test: t_sp_new_new -> ok
[83]Test ../../techlibs/intel/cyclone10lp/cells_sim.v ->Test: t_init_9b1B_zeros_zero -> ok
[91][93][92][94]Test: t_sp_new_nc -> ok
[87]Test: t_sync_shared -> ok
Test: t_sp_arst_e_x -> ok
[95][96][97]Test: t_init_13b2B_val_any -> ok
Test: t_init_4b1B_x_any -> ok
Test: t_init_9b1B_zeros_any -> ok
Test: t_init_18b2B_val_no_undef -> ok
Test: t_sync_small_block_attr -> ok
 ok
[98]Test: t_sp_arst_v_0 -> ok
Test ../../techlibs/intel/max10/cells_sim.v ->[99]Test: t_init_4b1B_x_zero -> ok
Test: t_sync_trans_new_old -> ok
Test: t_clock_a4_wPOSrNEGsTrue -> ok
Test: t_sync_big_sdp -> ok
Test: t_sp_nc_nc_be -> ok
+ ./cxxrtl-test-value
Passed opt-bug1525.ys
+ run_subtest value_fuzz
+ local subtest=value_fuzz
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++
Test: t_sync_trans_new_none -> ok
Test: t_sp_nc_new -> ok
Test: t_sp_old_new -> ok
Test: t_ram_4b1B -> ok
Test: t_sync_trans_new_new -> ok
Test: t_init_4b1B_x_no_undef -> ok
Test: t_sp_nc_none -> ok
Test: local_loop_var -> ok
Test: t_clock_a4_wNEGrNEGsTrue -> ok
Test: t_sp_init_v_0_re -> ok
Test: t_sp_old_nc -> ok
Test: t_sp_arst_v_x_re -> ok
 ok
Test: t_sp_new_old -> ok
Test: t_sp_old_new_only -> ok
Passed efinix-counter.ys
Test: t_sp_old_none -> ok
Test: t_init_9b1B_val_any -> ok
Test ../../techlibs/intel_alm/cyclonev/cells_sim.v ->Test: t_mixed_4_2 -> ok
 ok
Test: t_sp_new_auto_be -> ok
Passed efinix-dffs.ys
Test: t_sp_new_new_only -> ok
Test: t_ram_1b1B -> ok
Test: t_clock_a4_wNEGrNEGsFalse -> ok
Test: t_sp_arst_0_init -> ok
Test: t_ram_2b1B -> ok
Test: t_mixed_9_18 -> ok
Test: t_sp_init_0_0 -> ok
Test: t_sp_nc_new_only_be -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test ../../techlibs/microchip/cells_sim.v ->Test: t_sp_nc_auto -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_init_x_x -> ok
Test: t_sp_init_0_x -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_arst_n_x_re -> ok
Test: t_clock_a4_wANYrNEGsFalse -> ok
Test: t_sp_new_none -> ok
Test: t_sp_init_v_any -> ok
Test: t_sp_old_old -> ok
Test: t_sp_arst_e_0 -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_arst_x_x -> ok
 ok
Test: t_sp_init_v_x_re -> ok
Test: t_init_9b1B_val_zero -> ok
Warning: Complex async reset for dff `\q [12]'.
Warning: Complex async reset for dff `\q [8]'.
Test: t_sp_arst_0_init_re -> ok
Test: t_sp_arst_n_any -> ok
Test ../../techlibs/nanoxplore/cells_sim.v ->Test: t_sp_old_auto_be -> ok
Test: t_sp_old_auto -> ok
Test: t_sp_old_new_only_be -> ok
Test: t_sp_new_new_be -> ok
Test: t_sp_init_v_any_re -> ok
Test: t_sp_srst_0_x_re -> ok
Test: t_sp_init_v_0 -> ok
Test: t_unmixed -> ok
 ok
Test: t_mixed_18_9 -> ok
Test: t_sp_arst_n_x -> ok
Test ../../techlibs/nexus/cells_sim.v ->Test: t_sp_srst_e_any -> ok
Passed anlogic-add_sub.ys
Test: t_clock_a4_wNEGrPOSsFalse -> ok
Test: t_sp_nc_new_be -> ok
Test: t_sp_arst_x_x_re -> ok
Test: t_sp_arst_e_any -> ok
Test: t_sp_nc_auto_be -> ok
Test: t_sp_arst_0_x -> ok
Test: t_sp_arst_v_init_re -> ok
Test: t_sp_arst_0_0_re -> ok
Passed efinix-tribuf.ys
Test: t_sp_old_new_be -> ok
Test: t_sp_srst_gv_0 -> ok
Test: t_sp_new_old_be -> ok
Test: t_sp_arst_n_0 -> ok
Passed opt-bug1758.ys
Test: t_sp_srst_gv_any -> ok
Test: t_sp_srst_v_init -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed opt-bug1854.ys
Test: t_wren_a4d8w2_W16_B4_separate -> ok
Test: t_sp_srst_0_init -> ok
Test: t_sp_arst_n_any_re -> ok
Test: t_sp_arst_e_x_re -> ok
Test: t_sp_arst_0_any_re -> ok
Passed sat-dff.ys
Test: t_sp_srst_x_x -> ok
Test: t_sp_init_0_x_re -> ok
Test: t_sp_arst_0_0 -> ok
Test: t_sp_new_nc_be -> ok
Passed svtypes-logic_rom.ys
Test: t_sp_srst_e_init -> ok
Test: t_sp_srst_gv_any_re_gated -> ok
Test: t_sp_arst_v_init -> ok
Passed ice40-ice40_dsp.ys
Test: t_sync_trans_old_new -> ok
Test: t_sp_arst_e_init -> ok
Passed svtypes-enum_simple.ys
sh: line 1: vcd2fst: command not found
ERROR: Shell command failed!
Test: t_sync_trans_old_none -> ok
Test: t_wren_a4d8_W8_B8 -> ok
 ok
make[1]: *** [run-test.mk:6: sim-assume_x_first_step.ys] Error 1
make[1]: *** Waiting for unfinished jobs....
Passed machxo2-add_sub.ys
Test: t_clock_a4_wNEGrPOSsTrue -> ok
Test: t_sp_arst_v_any_re -> ok
Passed opt-bug2010.ys
Passed sat-counters.ys
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Passed anlogic-logic.ys
Passed sim-sim_adlatch.ys
Passed svtypes-static_cast_negative.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
<<EOT:1: ERROR: Static cast is only supported in SystemVerilog mode.
Expected error pattern 'Static cast is only supported in SystemVerilog mode' found !!!
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1934_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1952_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1943_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Test: t_sp_init_0_any_re -> ok
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1949_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1925_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1937_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1928_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1946_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1931_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1940_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap\_4_.$procdff$1955_gate ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1934_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1952_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1943_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Test: t_wren_a4d8w2_W8_B8_separate -> ok
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1949_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1925_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1937_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1928_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1946_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1931_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1940_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Warning: No SAT model available for async FF cell $techmap$mul$<<EOT:2$1.$procdff$1955_gold ($adff).  Consider running `async2sync` or `clk2fflogic` first.
Test: t_sync_2clk -> ok
Test: t_sp_srst_gv_any_ce -> ok
Test: t_wren_a4d8_W8_B4_separate -> ok
Passed efinix-logic.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed machxo2-shifter.ys
Test: t_geom_a7d11_9b1B -> ok
Passed sim-sim_adffe.ys
Passed anlogic-counter.ys
Passed svtypes-static_cast_verilog.ys
Test: t_sp_srst_gv_any_re -> ok
Test: t_wren_a4d4w2_W8_B4_separate -> ok
Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15.
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21.
Passed ecp5-bug1630.ys
Test: t_wren_a6d4_NO_BYTE -> ok
Warning: Complex async reset for dff `\Q'.
Test: t_sp_old_old_be -> ok
Test: t_sp_srst_n_x -> ok
Test: t_clock_a4_wPOSrPOSsTrue -> ok
<<EOT:7: ERROR: Insufficient number of array indices for a.
Expected error pattern 'Insufficient number of array indices for a.' found !!!
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_srst_x_x_re -> ok
Passed opt-bug2765.ys
Test: t_sp_srst_n_x_re -> ok
Passed opt-bug2221.ys
Test: t_wide_sdp_a7r2w0b0x0 -> ok
Passed svtypes-multirange_subarray_access.ys
Test: code_verilog_tutorial_counter -> ok
Test: t_sp_srst_gv_any_ce_gated -> ok
Test: t_sp_srst_v_0 -> ok
Test ../../techlibs/quicklogic/pp3/cells_sim.v ->Test: t_sp_old_nc_be -> ok
Test: t_sp_srst_v_any_ce_gated -> ok
<<EOT:1: ERROR: Static cast with non constant expression!
Expected error pattern 'Static cast with non constant expression' found !!!
Test: t_tdp -> ok
Test: t_sp_srst_v_x -> ok
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Test: t_sp_new_auto -> ok
Passed svtypes-static_cast_nonconst.ys
Test: t_geom_a5d64_wren -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed svtypes-static_cast_zero.ys
Test: t_sp_arst_v_0_re -> ok
ERROR: FF myDFFP.$auto$ff.cc:266:slice$671 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination
Expected error pattern 'unsupported initial value and async reset value combination' found !!!
Passed ecp5-opt_lut_ins.ys
 ok
Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v ->Test: t_wren_a4d16w1_W16_B4_separate -> ok
Passed opt-bug2318.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Async reset value `\ad' is not constant!
Passed gowin-init-error.ys
Test: t_wren_a4d4w5_W4_B4 -> ok
Passed efinix-shifter.ys
Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19.
Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19.
Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19.
Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19.
Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19.
Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19.
Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19.
Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19.
Passed ice40-ice40_wrapcarry.ys
Passed opt-bug2920.ys
Passed efinix-adffs.ys
Passed sat-asserts.ys
Passed intel_alm-blockram.ys
Warning: Complex async reset for dff `\Q'.
Passed sat-initval.ys
Test: t_sp_srst_n_0_re -> ok
Passed opt-bug2766.ys
 ok
Passed ice40-ice40_dsp_const.ys
Test: t_geom_a5d32_wren -> ok
Test: t_sp_srst_e_0 -> ok
Warning: Complex async reset for dff `\Q'.
Test ../../techlibs/quicklogic/common/cells_sim.v ->Warning: Ignoring boxed module dffepc.
Test: t_geom_a6d4_9b1B -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_wren_a4d4w1_W8_B8_separate -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_init_x_x_ce -> ok
Test: t_sp_srst_e_any_re -> ok
Passed svtypes-typedef_initial_and_assign.ys
Test: t_geom_a7d8_wren -> ok
Passed sim-sim_aldffe.ys
Passed sat-bug2595.ys
Test: sign_part_assign -> ok
 ok
Test: t_geom_a4d18_9b1B -> ok
Test: t_sp_arst_v_any -> ok
Test: t_sp_srst_gv_init_re -> ok
Passed opt-bug3047.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Test: t_wren_a4d4w4_W8_B4 -> ok
Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop.
Test: t_sp_srst_v_0_re -> ok
Test ../../techlibs/sf2/cells_sim.v ->Test: t_sp_arst_e_init_re -> ok
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Test: t_wide_sdp_a7r1w1b1x1 -> ok
Test: t_wide_sdp_a6r0w2b2x0 -> ok
Test: t_wren_a4d4w5_W4_B4_separate -> ok
Test: t_geom_a3d18_9b1B -> ok
Test: t_geom_a6d64_wren -> ok
Passed verilog-absurd_width.ys
Test: t_sp_arst_n_init_re -> ok
Passed verilog-always_comb_latch_1.ys
Passed opt-bug3867.ys
Warning: wire '\Q' is assigned in a block at <<EOT:9.5-9.11.
Warning: wire '\Q' is assigned in a block at <<EOT:11.5-11.11.
Passed svtypes-typedef_memory_2.ys
Warning: Async reset value `\ad' is not constant!
 ok
Warning: Feature 'write_aiger2' is experimental.
Passed sat-counters-repeat.ys
Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25.
Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Test: t_wren_a4d2w8_W16_B4_separate -> ok
Test: t_sp_srst_n_init -> ok
Test: t_geom_a4d4_9b1B -> ok
Test: t_wren_a4d4w4_W16_B4_separate -> ok
Passed svtypes-typedef_memory.ys
Passed sat-sizebits.ys
Test ../../techlibs/xilinx/cells_sim.v ->Warning: reg '\Q' is assigned in a continuous assignment at <<EOT:9.9-9.19.
Test: t_sp_srst_v_any_re -> ok
Test: t_wide_sdp_a8r1w1b1x1 -> ok
Passed pp3-add_sub.ys
Passed opt-bug2623.ys
Test: t_sp_init_x_x_re -> ok
Test: t_wren_a4d4w4_W8_B4_separate -> ok
Test: t_wren_a5d8w2_W16_B4 -> ok
Test: t_wren_a4d4_W4_B4 -> ok
Passed techmap-adff2dff.ys
Passed sim-sim_dffe.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed sim-sim_adff.ys
Passed opt-bug2311.ys
Passed efinix-fsm.ys
Passed svtypes-multirange_array.sv
Test: t_wren_a5d4_NO_BYTE -> ok
Warning: reg '\QQQ' is assigned in a continuous assignment at <<EOT:5.9-5.16.
Passed efinix-lutram.ys
Passed sat-splice.ys
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Test: t_sp_srst_0_init_re -> ok
Passed opt-bug2824.ys
Test: t_wide_write_a6r2w0b0 -> ok
Test: t_wren_a5d4w2_W16_B4_separate -> ok
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16.
Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21.
Warning: Wire top.\cnt [7] is used but has no driver.
Warning: Wire top.\cnt [6] is used but has no driver.
Warning: Wire top.\cnt [5] is used but has no driver.
Warning: Wire top.\cnt [4] is used but has no driver.
Warning: Wire top.\cnt [3] is used but has no driver.
Warning: Wire top.\cnt [2] is used but has no driver.
Warning: Wire top.\cnt [1] is used but has no driver.
Warning: Wire top.\cnt [0] is used but has no driver.
Test: t_wide_sp_mix_a7r0w1b0 -> ok
Test: t_wide_sp_tied_a6r0w1b0 -> ok
Test: t_wren_a5d8w1_W16_B4_separate -> ok
Test: t_sp_nc_old_be -> ok
Passed sat-grom.ys
Passed svtypes-typedef_struct_port.ys
Passed intel_alm-shifter.ys
Test: t_sp_srst_v_any -> ok
Test: t_geom_a6d30_wren -> ok
Passed sat-expose_dff.ys
Test: t_sp_arst_v_x -> ok
Test: t_wide_sdp_a7r0w1b0x0 -> ok
 ok
Test ../../techlibs/common/simcells.v ->Passed verilog-absurd_width_const.ys
Test: t_sp_new_new_only_be -> ok
Test: t_wide_sp_tied_a7r1w0b0 -> ok
Test: t_wide_sdp_a6r0w3b2x0 -> ok
Passed opt-bug5164.ys
Passed various-abstract_init.ys
Test: t_sp_init_v_x -> ok
Passed various-abstract_value.ys
Test: t_wren_a4d4w2_W8_B4 -> ok
Test: t_wren_a5d4w4_W16_B4_separate -> ok
Passed gowin-logic.ys
Test: t_sp_srst_0_0 -> ok
Test: t_wren_a3d8_NO_BYTE -> ok
Test: t_geom_a7d6_wren -> ok
Warning: Complex async reset for dff `\q'.
Passed sim-sim_cycles.ys
Test: t_wren_a4d8w2_W8_B8 -> ok
Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits.
Passed sat-asserts_seq.ys
Test: t_sp_init_0_any -> ok
Test: t_sp_srst_gv_init -> ok
Passed memory_bram test 00_04.
Test: t_wren_a5d4w2_W16_B4 -> ok
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Test: t_wide_sdp_a7r0w4b2x0 -> ok
Passed opt-bug3848.ys
Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000'
ERROR: Signal difference
Expected error pattern 'Signal difference' found !!!
Test: t_wren_a4d8_NO_BYTE -> ok
Test: t_geom_a9d6_wren -> ok
Test: t_wide_sp_tied_a6r0w2b0 -> ok
Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
Test: t_wide_write_a7r0w1b1 -> ok
Test: t_sp_arst_0_any -> ok
Passed memory_bram test 00_03.
Passed sat-sim_counter.ys
Test: t_wide_read_a6r3w0b0 -> ok
Test: t_wide_sp_tied_a7r0w1b0 -> ok
Test: t_wide_sp_tied_a6r4w0b0 -> ok
Passed ecp5-add_sub.ys
Passed opt-bug4610.ys
Passed various-attrib07_func_call.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed verilog-always_comb_latch_2.ys
Test: t_wide_quad_a5w2r1 -> ok
Passed sim-sim_aldff.ys
Test: t_sp_srst_v_any_re_gated -> ok
Test: t_sp_srst_v_x_re -> ok
Test: code_verilog_tutorial_fsm_full -> ok
Test: t_wide_sdp_a6r0w2b0x0 -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_sp_srst_0_x -> ok
Passed anlogic-shifter.ys
Test: t_sp_arst_n_0_re -> ok
Test: t_sp_srst_gv_x_re -> ok
Test: t_wren_a4d2w8_W16_B4 -> ok
Test: t_sp_srst_e_x_re -> ok
Test: t_wren_a3d8w2_W8_B8_separate -> ok
Test: t_geom_a7d4_wren -> ok
Passed verilog-always_comb_nolatch_2.ys
Test: t_sp_srst_e_0_re -> ok
Test: t_sp_srst_n_init_re -> ok
Test: t_wide_sdp_a6r0w0b0x0 -> ok
Passed svtypes-static_cast_simple.sv
Test: t_wren_a4d8_W4_B4_separate -> ok
Passed various-abstract_state.ys
Test: t_wide_sdp_a7r0w0b0x0 -> ok
Test: t_wren_a3d8w2_W8_B8 -> ok
 ok
Test ../../techlibs/common/simlib.v ->Test: t_sp_arst_e_0_re -> ok
Test: t_wide_sp_mix_a7r0w1b1 -> ok
Test: t_sp_srst_0_any_re -> ok
Test: t_wide_sp_mix_a7r0w3b2 -> ok
Passed svtypes-typedef_struct_global.ys
Test: t_wide_sp_tied_a7r2w0b0 -> ok
Test: t_wren_a4d4w1_W8_B8 -> ok
Test: t_sp_srst_0_0_re -> ok
Test: t_wide_write_a7r1w1b1 -> ok
Test: t_sp_init_0_0_re -> ok
Test: t_wide_sp_mix_a7r1w1b1 -> ok
Test: t_wide_oct_a4w2r3 -> ok
Test: t_wide_sdp_a7r3w0b0x0 -> ok
Test: t_sp_srst_gv_0_re -> ok
Passed various-aiger_dff.ys
Warning: Feature 'bufnorm' is experimental.
Passed opt-memory_bmux2rom.ys
Test: t_sp_srst_v_any_ce -> ok
ERROR: Latch inferred for signal `\top.$unnamed_block$3.y' from always_comb process `\top.$proc$<<EOF:0$4'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process' found !!!
Passed opt-bug4413.ys
Test: t_wide_sp_mix_a6r0w2b2 -> ok
Test: t_wren_a4d2w4_W8_B4 -> ok
Test: t_wide_oct_a4w2r1 -> ok
Test: t_sp_srst_n_0 -> ok
Passed verilog-always_comb_latch_4.ys
Passed opt-bug3117.ys
Test: t_wide_write_a7r2w0b0 -> ok
Passed various-autoname.ys
Passed techmap-autopurge.ys
Passed techmap-bufnorm.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed opt-opt_clean_init.ys
Passed anlogic-tribuf.ys
Passed verilog-always_comb_nolatch_1.ys
struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef.
struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef.
struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef.
struct_array.sv:45: Warning: Range [3:-4] select out of bounds on signal `\s_s': Setting 4 LSB bits to undef.
struct_array.sv:46: Warning: Range select [23:16] out of bounds on signal `\s_s': Setting all 8 result bits to undef.
struct_array.sv:47: Warning: Range [19:12] select out of bounds on signal `\s_s': Setting 4 MSB bits to undef.
struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef.
struct_array.sv:38: Warning: Range [-1:-8] select out of bounds on signal `\s_s': Setting 8 LSB bits to undef.
Test: t_sp_arst_e_any_re -> ok
Passed svtypes-struct_simple.sv
Test: t_sp_arst_n_init -> ok
Test: t_wide_sp_mix_a6r5w0b0 -> ok
Passed verilog-always_comb_latch_3.ys
Test: t_sp_srst_0_any -> ok
Passed sim-sim_dffsr.ys
Test: t_wide_oct_a4w4r1 -> ok
Test: t_sp_nc_old -> ok
Test: t_wide_write_a6r0w0b0 -> ok
Test: t_wide_sp_mix_a7r0w5b2 -> ok
Test: t_sp_srst_n_any -> ok
Test: t_wide_sp_tied_a7r0w0b0 -> ok
Test: t_wren_a4d16w1_W16_B4 -> ok
Test: t_wide_read_a7r0w1b0 -> ok
Test: t_sp_srst_n_any_re -> ok
Test: t_sp_srst_e_x -> ok
Test: t_sp_srst_gv_x -> ok
Test: t_wide_sdp_a6r0w1b0x0 -> ok
Test: t_wren_a4d4_NO_BYTE -> ok
Passed verilog-always_comb_nolatch_3.ys
Test: t_wren_a5d4w4_W16_B4 -> ok
Passed techmap-bmuxmap_pmux.ys
 ok
Test: t_wide_sp_mix_a6r1w0b0 -> ok
Test: t_wren_a4d4w4_W4_B4 -> ok
Test: t_wide_sp_mix_a7r0w4b2 -> ok
...passed tests in tests/arch
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed various-box_derive.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed sim-sim_sdffce.ys
Test: t_wide_sp_mix_a7r5w0b0 -> ok
Test: t_wide_read_a7r0w0b0 -> ok
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_wide_sp_tied_a6r1w1b1 -> ok
Test: t_wide_write_a6r4w0b0 -> ok
Passed various-blackbox_wb.ys
<<EOT:19: Warning: Range select [13:12] out of bounds on signal `\Q': Setting all 2 result bits to undef.
<<EOT:20: Warning: Range select [15:14] out of bounds on signal `\Q': Setting all 2 result bits to undef.
Test: t_wide_sdp_a7r0w2b2x0 -> ok
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Test: t_wide_read_a6r1w1b1 -> ok
Passed verilog-always_comb_nolatch_4.ys
Test: t_wide_sdp_a7r5w0b0x0 -> ok
Test: t_wide_quad_a4w4r6 -> ok
Test: t_wide_sp_mix_a7r1w0b0 -> ok
Test: t_sp_srst_v_init_re -> ok
Passed verilog-asgn_expr_not_proc_2.ys
Test: t_wren_a4d8w2_W16_B4 -> ok
Test: t_geom_a5d32_9b1B -> ok
Test: t_sp_srst_e_init_re -> ok
Passed sim-sim_sdff.ys
Test: t_wide_sdp_a6r1w0b0x0 -> ok
Test: t_rom_case -> ok
Test: t_wide_sp_tied_a6r0w2b2 -> ok
Passed techmap-bug2183.ys
Test: t_sp_arst_0_x_re -> ok
Passed sim-sim_dlatchsr.ys
Passed verilog-always_comb_nolatch_5.ys
Test: t_wren_a5d8w1_W16_B4 -> ok
Passed svtypes-typedef_simple.sv
Passed pp3-logic.ys
Passed svtypes-typedef_param.sv
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:2)
Passed sim-sim_sdffe.ys
Test: t_wide_read_a6r0w5b2 -> ok
Passed various-aiger2.ys
Test: t_wren_a4d2w4_W8_B4_separate -> ok
Test: t_wide_read_a7r5w0b0 -> ok
Test: t_wide_sp_tied_a7r0w2b0 -> ok
Test: t_wide_sp_mix_a6r0w1b1 -> ok
Passed intel_alm-add_sub.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Test: t_wren_a4d4w2_W8_B8 -> ok
Test: realexpr -> ok
Passed ecp5-macc.ys
Test: t_wide_sdp_a7r0w3b2x0 -> ok
Test: t_wide_read_a6r0w0b0 -> ok
Test: t_wide_read_a7r0w4b2 -> ok
Test: t_wide_sp_mix_a6r0w2b0 -> ok
Test: t_wide_sp_tied_a6r5w0b0 -> ok
Passed ecp5-bug2731.ys
Test: t_gclken -> ok
Passed opt-opt_clean_mem.ys
Test: t_wide_read_a7r1w0b0 -> ok
Passed ecp5-bug1598.ys
Test: t_wide_sdp_a6r0w4b2x0 -> ok
Passed svtypes-typedef_struct.sv
Test: t_wide_sp_mix_a6r0w0b0 -> ok
Test: t_exclwr -> ok
Test: t_wide_sdp_a6r1w1b1x1 -> ok
Test: t_wide_sdp_a7r4w0b0x0 -> ok
Passed svtypes-struct_sizebits.sv
Test: t_wide_quad_a4w2r6 -> ok
Passed svtypes-struct_dynamic_range.ys
Passed sim-sim_dlatch.ys
Test: t_rom_case_block -> ok
Test: t_wide_sp_mix_a7r0w0b0 -> ok
Passed pp3-counter.ys
Test: t_wide_sp_mix_a6r1w1b1 -> ok
Test: t_wren_a4d8_W8_B8_separate -> ok
Test: t_wide_oct_a4w2r2 -> ok
Passed svtypes-union_simple.sv
Test: t_wide_write_a7r1w0b0 -> ok
Passed techmap-buf.ys
Passed sim-sim_dff.ys
Test: t_geom_a11d1_9b1B -> ok
Test: t_wide_sdp_a6r3w0b0x0 -> ok
Passed various-attrib05_port_conn.ys
Test: t_wide_quad_a4w4r4 -> ok
Test: t_geom_a7d17_wren -> ok
Test: t_wide_quad_a4w4r1 -> ok
Test: t_wide_sp_tied_a6r3w0b0 -> ok
Test: t_quad_port_a6d2 -> ok
Passed various-bug1496.ys
Passed various-bug1710.ys
Test: t_wren_a4d8_W8_B4 -> ok
Test: t_wide_oct_a4w2r4 -> ok
sh: line 1: vcd2fst: command not found
ERROR: Shell command failed!
Passed machxo2-counter.ys
Test: t_geom_a4d64_wren -> ok
make[1]: *** [run-test.mk:81: sim-vcd_var_reference_whitespace.ys] Error 1
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/sim'
Test: t_wren_a5d8w2_W16_B4_separate -> ok
Test: t_wide_sp_mix_a7r4w0b0 -> ok
make: *** [Makefile:935: makefile-tests/tests/sim] Error 2
make: *** Waiting for unfinished jobs....
Test: t_wide_sp_tied_a6r0w1b1 -> ok
Passed opt-opt_dff_dffmux.ys
Test: t_wide_sp_tied_a7r0w2b2 -> ok
Test: t_wide_oct_a4w2r5 -> ok
Test: t_wide_sp_mix_a6r0w4b2 -> ok
Test: t_wide_sdp_a6r2w0b0x0 -> ok
Test: t_wide_quad_a4w2r3 -> ok
Test: t_wide_write_a8r1w1b1 -> ok
Test: t_wide_sp_tied_a6r0w0b0 -> ok
Test: t_wide_read_a7r0w2b2 -> ok
Test: t_wide_read_a7r1w1b1 -> ok
Test: t_wide_quad_a4w2r2 -> ok
Test: t_wide_sdp_a6r4w0b0x0 -> ok
Test: t_wide_oct_a5w2r9 -> ok
Test: t_wide_sdp_a6r0w1b1x0 -> ok
Test: t_wide_read_a7r2w0b0 -> ok
Test: t_wide_write_a7r0w3b2 -> ok
xprop_eqx_5u3_2: ok
Passed svtypes-typedef_package.sv
Passed gowin-compare.ys
Passed opt-opt_dff_clk.ys
xprop_eqx_5u3_2: ok
Passed techmap-bug2321.ys
Test: t_wide_sp_mix_a7r0w2b0 -> ok
Passed verilog-always_comb_nolatch_6.ys
Test: t_wide_sdp_a7r1w0b0x0 -> ok
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Test: t_wr_rst_byte -> ok
Test: t_geom_a6d16_wren -> ok
Test: t_wide_sp_mix_a6r4w0b0 -> ok
Test: t_wide_read_a7r3w0b0 -> ok
Passed pp3-tribuf.ys
Test: t_wren_a4d4w2_W8_B8_separate -> ok
Test: t_wide_read_a6r0w2b0 -> ok
Passed techmap-cellname.ys
Passed verilog-asgn_expr_not_proc_1.ys
Test: t_geom_a7d18_9b1B -> ok
Test: t_wide_quad_a4w2r9 -> ok
Test: t_geom_a9d8_wren -> ok
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
<<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
Test: t_wide_quad_a4w4r9 -> ok
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed svtypes-struct_array.sv
Test: t_wren_a4d4w4_W16_B4 -> ok
Test: t_excl_rst -> ok
Test: t_wide_read_a6r0w1b1 -> ok
Passed techmap-bug2332.ys
Passed verilog-asgn_expr_not_proc_5.ys
Passed various-bug1876.ys
Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Warning: wire '\Q' is assigned in a block at <<EOT:8.3-8.9.
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0
Passed memory_bram test 02_00.
xprop_le_5u3_2: ok
Test: t_wide_sdp_a7r0w2b0x0 -> ok
xprop_le_5u3_2: ok
Test: t_wide_oct_a4w2r9 -> ok
Test: t_geom_a8d4_wren -> ok
Test: t_wide_sdp_a7r0w1b1x0 -> ok
Passed svtypes-typedef_scopes.sv
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/svtypes'
Passed techmap-constmap.ys
...passed tests in tests/svtypes
Test: t_wide_write_a6r0w3b2 -> ok
Test: t_geom_a8d6_wren -> ok
Test: t_geom_a9d5_wren -> ok
Test: t_wide_quad_a4w2r4 -> ok
Passed various-bug1745.ys
Passed verilog-asgn_expr_not_proc_3.ys
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0
Passed techmap-dffinit.ys
Passed verilog-asgn_expr_not_proc_4.ys
Test: t_wide_quad_a4w2r1 -> ok
Test: t_wide_sp_tied_a7r1w1b1 -> ok
Passed gowin-counter.ys
Test: t_wide_sp_mix_a6r2w0b0 -> ok
Test: t_wide_sp_mix_a6r0w1b0 -> ok
Test: t_wide_sp_tied_a7r3w0b0 -> ok
Running macc_b_port_compat.ys..
Passed gatemate-add_sub.ys
Test: t_wide_write_a7r4w0b0 -> ok
Passed various-bug2014.ys
Passed various-bug4082.ys
Passed intel_alm-dffs.ys
Test: t_wren_a4d4w4_W4_B4_separate -> ok
Test: t_quad_port_a5d2 -> ok
Warning: Shift register inference not yet supported for family xc3se.
Passed various-bug1614.ys
Test: t_wide_sp_mix_a6r0w5b2 -> ok
Passed intel_alm-logic.ys
Passed various-bug1781.ys
Test: t_wide_write_a7r0w0b0 -> ok
Test: t_wide_sp_tied_a7r0w3b2 -> ok
Test: t_wide_write_a6r0w5b2 -> ok
Test: t_wide_write_a7r0w5b2 -> ok
Passed techmap-cellmatch.ys
Test: t_wide_sp_mix_a8r1w1b1 -> ok
Test: t_wide_sp_mix_a7r3w0b0 -> ok
Passed memory_bram test 03_01.
Test: t_quad_port_a2d2 -> ok
Test: t_gclken_ce -> ok
Passed various-bug3462.ys
Test: t_wide_oct_a5w2r1 -> ok
Test: t_geom_a9d4_wren -> ok
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Test: t_wide_write_a6r0w4b2 -> ok
Test: t_wide_sdp_a6r5w0b0x0 -> ok
Passed techmap-clockgate.ys
Test: t_wide_sp_tied_a6r0w5b2 -> ok
Passed pp3-dffs.ys
Test: t_wide_write_a6r1w0b0 -> ok
Test: t_wide_read_a7r4w0b0 -> ok
Test: t_wide_sp_tied_a7r0w1b1 -> ok
Test: t_wide_sp_tied_a6r0w4b2 -> ok
Test: t_wide_sp_tied_a6r2w0b0 -> ok
Test: t_wide_sp_tied_a7r5w0b0 -> ok
xprop_le_5s3_2: ok
Passed opt-opt_expr_cmp.ys
Passed verilog-asgn_expr_not_sv_1.ys
Passed memory_bram test 01_03.
xprop_le_5s3_2: ok
Passed techmap-dff2ff.ys
xprop_dffe_3npd: ok
Test: t_wide_sp_mix_a7r2w0b0 -> ok
Passed gatemate-shifter.ys
Passed various-bug4865.ys
xprop_dffe_3npd: ok
Passed various-bug3879.ys
Test: t_wide_quad_a4w2r8 -> ok
Warning: Wire top.\y [11] is used but has no driver.
Warning: Wire top.\y [10] is used but has no driver.
Warning: Wire top.\y [9] is used but has no driver.
Warning: Wire top.\y [8] is used but has no driver.
Warning: Wire top.\y [7] is used but has no driver.
Warning: Wire top.\y [6] is used but has no driver.
Warning: Wire top.\y [5] is used but has no driver.
Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [3] is used but has no driver.
Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [2] is used but has no driver.
Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [1] is used but has no driver.
Warning: Wire top.$auto$bugpoint.cc:258:simplify_something$12 [0] is used but has no driver.
Warning: Wire top.$delete_wire$14 is used but has no driver.
Test: t_wide_write_a6r0w1b0 -> ok
Test: t_wide_oct_a4w2r6 -> ok
Passed opt-opt_expr_consumex.ys
Test: t_wide_quad_a4w2r7 -> ok
Warning: Complex async reset for dff `\Q'.
Warning: Ignoring boxed module dffepc.
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Warning: wire '\a' is assigned in a block at <<EOT:4.2-4.8.
Warning: wire '\a' is assigned in a block at <<EOT:5.2-5.8.
Test: t_wide_read_a6r0w1b0 -> ok
Warning: found logic loop in module top:
    cell $xor$<<EOF:6$2 ($xor) source: <<EOF:6.18-6.59
      A[0] --> Y[0]
    wire \ripple [0] source: <<EOF:2.13-2.19
Passed various-cellarray_array_connections.ys
ERROR: Found 1 problems in 'check -assert'.
Expected error pattern 'Found 1 problems in 'check -assert'' found !!!
Test: t_wide_sp_tied_a8r1w1b1 -> ok
Test: t_wide_sp_tied_a6r1w0b0 -> ok
Test: t_wide_sp_mix_a6r3w0b0 -> ok
Test: t_wide_quad_a4w2r5 -> ok
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed verilog-asgn_expr_not_sv_2.ys
Passed memory_bram test 01_00.
Passed various-check_2.ys
Passed opt-opt_expr_and.ys
Passed intel_alm-tribuf.ys
Test: t_grden_ce -> ok
Test: t_wide_read_a7r0w1b1 -> ok
Warning: found logic loop in module top:
    cell $auto$memory_dff.cc:512:handle_rd_port$62 ($logic_not)
      A[0] --> Y[0]
    cell $memrd$\mem$<<EOF:15$20 ($memrd_v2) source: <<EOF:15.12-15.15
      ARST[0] --> DATA[0]
    wire \data [0] source: <<EOF:1.68-1.72
ERROR: Found 1 problems in 'check -assert'.
Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!!
Passed various-bug4909.ys
Warning: wire '\a' is assigned in a block at <<EOT:4.9-4.15.
Warning: wire '\a' is assigned in a block at <<EOT:5.9-5.15.
Passed gatemate-tribuf.ys
Warning: wire '\a_q' is assigned in a block at <<EOT:7.9-7.17.
Warning: wire '\en_q' is assigned in a block at <<EOT:8.9-8.19.
Passed verilog-asgn_expr_not_sv_3.ys
Test: t_trans_rst -> ok
Passed gowin-tribuf.ys
Test: t_wide_read_a7r0w5b2 -> ok
Test: t_wide_sp_tied_a6r0w3b2 -> ok
Passed ice40-add_sub.ys
Test: t_wide_write_a7r0w2b2 -> ok
Passed various-check_4.ys
Passed opt-opt_expr_constconn.ys
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[2] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
Test: t_grden -> ok
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[2] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[3] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[3] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[0] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[0] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0
Test: t_wide_write_a6r1w1b1 -> ok
Passed various-bug1531.ys
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[6] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[6] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[7] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[7] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Test: t_wide_write_a6r0w2b0 -> ok
ERROR: Cannot use both -assert2assume and -assert2cover.
Expected error pattern 'Cannot use both' found !!!
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[4] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[4] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Test: t_wide_read_a6r2w0b0 -> ok
ERROR: Found 8 problems in 'check -assert'.
Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!!
Passed techmap-dfflegalize_adlatch.ys
Warning: Ignoring boxed module dffepc.
Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop.
Passed opt-opt_expr_mux_undef.ys
Test: t_wide_write_a7r5w0b0 -> ok
Passed techmap-clkbufmap.ys
Test: t_wide_read_a7r0w2b0 -> ok
Test: t_wide_write_a7r0w2b0 -> ok
Passed various-chformal_check.ys
Test: t_wide_read_a8r1w1b1 -> ok
<<EOT:2: ERROR: syntax error, unexpected TOK_BASE
Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
Test: t_wide_oct_a4w4r6 -> ok
<<EOF:3: ERROR: syntax error, unexpected TOK_ID
Expected error pattern 'syntax error, unexpected TOK_ID' found !!!
Passed various-check_3.ys
Test: t_wide_sp_mix_a7r0w2b2 -> ok
Test: t_wide_sp_tied_a7r0w4b2 -> ok
Test: t_wide_oct_a4w2r7 -> ok
Test: t_wide_oct_a5w2r4 -> ok
Passed various-constcomment.ys
Test: t_wide_read_a6r1w0b0 -> ok
Passed techmap-aigmap.ys
Passed verilog-asgn_expr_not_sv_4.ys
Test: t_wide_read_a7r0w3b2 -> ok
Passed techmap-bug2759.ys
Passed efinix-mux.ys
Test: t_no_reset -> ok
Passed opt-opt_dff_arst.ys
Test: t_rdenrst_wr_byte -> ok
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0
Test: t_wide_write_a6r3w0b0 -> ok
Passed opt-opt_dff_qd.ys
Passed opt-opt_expr_or.ys
Passed opt-opt_expr_shr_int_max.ys
Passed opt-opt_expr_alu.ys
Passed memory_bram test 02_04.
Test: t_quad_port_a4d8 -> ok
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff0
Passed various-check.ys
Warning: Drivers conflicting with a constant 1'1 driver:
    module input A[0]
Passed various-const_func_block_var.ys
Warning: Drivers conflicting with a constant 1'1 driver:
    port Y[0] of cell some_buffer (buffer)
Passed verilog-assign_to_reg.ys
Warning: reg '\Q' is assigned in a continuous assignment at <<EOT:5.9-5.14.
Test: t_wide_read_a6r0w3b2 -> ok
Warning: Drivers conflicting with a constant 1'1 driver:
    action \Q <= $0\Q[0:0] (sync rule) in process $proc$<<EOT:3$1
Warning: Ignoring boxed module $__PP3_DFFEPC_SYNCONLY_$abc9_flop.
Passed verilog-asgn_expr.ys
Passed various-chformal_coverenable.ys
Test: t_wide_write_a7r0w1b0 -> ok
Test: t_wide_oct_a4w2r8 -> ok
Passed opt-opt_lut_elim.ys
Passed various-constant_drive_conflict.ys
Running macc_infer_n_unmap.ys..
Test: t_wide_sp_mix_a6r0w3b2 -> ok
Passed opt-opt_expr_combined_assign.ys
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0
Test: t_wide_sp_tied_a7r4w0b0 -> ok
Test: t_wide_read_a6r4w0b0 -> ok
xprop_divfloor_5u3_3: ok
xprop_divfloor_5u3_3: ok
Test: t_wide_write_a7r0w4b2 -> ok
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff0
Passed techmap-bug2972.ys
Test: t_wide_read_a6r0w2b2 -> ok
Test: t_wide_read_a6r5w0b0 -> ok
Passed ice40-counter.ys
<<EOT:5: ERROR: Begin label (a) and end label (b) don't match.
Expected error pattern 'Begin label \(a\) and end label \(b\) don't match\.' found !!!
Test: t_wide_read_a6r0w4b2 -> ok
Passed memory_bram test 03_04.
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed ecp5-mul.ys
Passed xilinx-xilinx_dsp.ys
Passed verilog-block_labels.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_].
Passed opt-opt_lut_ins.ys
Test: t_wide_quad_a5w2r9 -> ok
Passed verilog-block_end_label_only.ys
Passed verilog-block_end_label_wrong.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
Passed opt-opt_lut_port.ys
Test: t_quad_port_a4d4 -> ok
Passed techmap-dfflegalize_adff.ys
Test: t_wide_write_a6r0w1b1 -> ok
xprop_dffe_3nnd: ok
xprop_dffe_3nnd: ok
Passed techmap-dfflegalize_dlatch.ys
Passed techmap-dfflegalize_aldff_init.ys
Passed memory_bram test 02_03.
Test: t_wr_byte -> ok
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_].
Test: t_rst_wr_byte -> ok
<<EOT:19: Warning: Range [6:-1] select out of bounds on signal `\in': Setting 1 LSB bits to undef.
<<EOT:19: Warning: Range [6:-1] select out of bounds on signal `\in': Setting 3 MSB bits to undef.
Passed various-const_arg_loop.ys
Passed opt-opt_expr.ys
Passed verilog-bug2037.ys
Passed verilog-atom_type_signedness.ys
Running boxes_equals_operators.ys..
...passed tests in tests/alumacc
Running boxes_equals_pattern.ys..
Passed various-constmsk_test.ys
Passed opt-opt_expr_shift.ys
Running boxes_equals_wildcard.ys..
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed techmap-dfflegalize_dlatchsr.ys
<<EOT:5: ERROR: Cannot add cell `\x' because a memory with the same name was already created at <<EOT:4.15-4.16!
Expected error pattern 'Cannot add cell `\\x' because a memory with the same name was already created' found !!!
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0
Running bug3374.ys..
Passed opt-memory_map_offset.ys
Passed ecp5-latches_abc9.ys
ERROR: Syntax error in line 1!
Expected error pattern 'Syntax error in line 1!' found !!!
Passed verilog-conflict_cell_memory.ys
Running bug3385.ys..
Test: t_wide_write_a6r5w0b0 -> ok
Passed various-design1.ys
Passed techmap-dfflegalize_mince.ys
Passed verilog-bug656.ys
ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals.
Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!!
Test: t_wide_write_a7r3w0b0 -> ok
Test: t_wide_sdp_a7r0w5b2x0 -> ok
Running boxes_import.ys..
Passed techmap-dfflegalize_minsrst.ys
...passed tests in tests/blif
Warning: Selection "wb" did not match any module.
ERROR: No top module found in source design.
Expected error pattern 'No top module found in source design\.' found !!!
Passed opt-opt_merge_keep.ys
Running boxes_no_equals_clean.ys..
Passed opt-opt_merge_init.ys
Warning: Selection "wb" did not match any module.
Test: t_wide_quad_a5w2r4 -> ok
Passed various-countbits.ys
<<EOT:5: ERROR: task/function argument direction missing
Expected error pattern 'task/function argument direction missing' found !!!
Passed gowin-add_sub.ys
Passed techmap-dfflegalize_dffsr.ys
Running boxes_no_equals.ys..
Test: t_wide_oct_a4w4r4 -> ok
Test: t_wide_oct_a4w4r9 -> ok
Passed verilog-bug2042.ys
Running boxes_setattr.ys..
xprop_shift_4u3s_3: ok
Test: t_quad_port_a4d2 -> ok
xprop_shift_4u3s_3: ok
Test: t_wide_sdp_a6r0w5b2x0 -> ok
<<EOT:4: ERROR: Cannot add procedural assertion `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add procedural assertion `\\x' because a signal with the same name was already created' found !!!
Test: t_wide_write_a6r0w2b2 -> ok
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:23)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:29)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:35)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:58)
<<EOT:0: ERROR: Cannot add interface port `\i' because a signal with the same name was already created at <<EOT:9.10-9.11!
Expected error pattern 'Cannot add interface port `\\i' because a signal with the same name was already created' found !!!
Passed verilog-conflict_assert.ys
Passed verilog-conflict_interface_port.ys
Passed opt-opt_expr_xnor.ys
Running boxes_stack.ys..
Passed various-cutpoint_blackbox.ys
Running internal_selects.ys..
Passed ecp5-bug1836.ys
<<EOT:3: Warning: Ignoring assignment to constant bits:
    old assignment: 2 = 1
    new assignment: { } = { }.
<<EOT:4: ERROR: Cannot add pwire `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add pwire `\\x' because a signal with the same name was already created' found !!!
Warning: Ignoring blackbox module bb.
Warning: Ignoring boxed module wb.
Warning: Ignoring boxed module bb.
Warning: Ignoring partially selected module wb.
Warning: Ignoring partially selected module top.
Passed techmap-dfflegalize_dlatch_init.ys
Running bug2619.ys..
Passed opt-opt_reduce_andor.ys
Running list_mod.ys..
Passed ice40-bug2061.ys
Warning: Complex async reset for dff `\Q'.
Running bug2656.ys..
Passed verilog-conflict_pwire.ys
elab_sys_tasks.sv:8: Warning: X is 1.
elab_sys_tasks.sv:22: Warning: 
Warning: wire '\q1' is assigned in a block at <<EOT:8.3-8.11.
Warning: wire '\q2' is assigned in a block at <<EOT:12.3-12.10.
Warning: wire '\q2' is assigned in a block at <<EOT:14.3-14.11.
<<EOT:6: ERROR: syntax error, unexpected TOK_ENDTASK, expecting ';'
Expected error pattern 'syntax error, unexpected TOK_ENDTASK, expecting ';'' found !!!
xprop_dff_3nd: ok
xprop_dff_3nd: ok
Passed various-cutpoint_whole.ys
Running bug2962.ys..
Passed various-elab_sys_tasks.ys
Passed verilog-bug2042-sv.ys
<<EOT:6: ERROR: Failed to detect width for identifier \genblk1.y!
Expected error pattern 'Failed to detect width for identifier \\genblk1\.y!' found !!!
Running bug4712.ys..
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:18)
Passed techmap-dfflegalize_sr.ys
Passed techmap-extractinv.ys
Passed verilog-bug2493.ys
Warning: Async reset value `\a_r' is not constant!
Running case_attr.ys..
Passed opt-opt_rmdff_sat.ys
Passed ecp5-bug1459.ys
<<EOT:3: ERROR: Cannot add signal `\x' because a memory with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add signal `\\x' because a memory with the same name was already created' found !!!
Warning: Complex async reset for dff `\q'.
Passed techmap-iopadmap.ys
Running mod-attribute.ys..
Test: t_ungated -> ok
Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver.
Passed various-equiv_opt_undef.ys
Passed verilog-conflict_wire_memory.ys
Passed opt-opt_pow.ys
Test: t_trans_byte -> ok
xprop_bmux_2_2: ok
Passed opt-opt_expr_xor.ys
Running no_warn_assert.ys..
Passed efinix-latches.ys
xprop_bmux_2_2: ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/efinix'
...passed tests in tests/arch/efinix
Running clean_undef_case.ys..
Passed verilog-const_sr.ys
Running no_warn_prefixed_arg_memb.ys..
Passed various-equiv_make_make_assert.ys
+ iverilog -o iverilog-initial_display initial_display.v
Running proc_dff.ys..
Passed verilog-const_arst.ys
Test: t_transwr -> ok
<<EOT:0: ERROR: Cell arrays of primitives are currently not supported.
Expected error pattern 'Cell arrays of primitives are currently not supported' found !!!
Running no_warn_prefixed_empty_select_arg.ys..
Warning: Complex async reset for dff `\q'.
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/simcells.v:476)
Passed verilog-bug4785.ys
Passed techmap-dfflegalize_dff.ys
Running unset2.ys..
Checking and_to_bad_out.aag.
ERROR: Selection @foo is not defined!
Expected error pattern 'Selection @foo is not defined!' found !!!
Running unset.ys..
+ ./iverilog-initial_display
Passed techmap-dfflibmap.ys
Passed machxo2-adffs.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_].
ERROR: Selection '\foo' does not exist!
Expected error pattern 'Selection '\\foo' does not exist!' found !!!
Running warn_empty_select_arg.ys..
+ diff yosys-initial_display.log iverilog-initial_display.log
Test: t_wide_sp_tied_a7r0w5b2 -> ok
Passed anlogic-lutram.ys
Warning: Selection "foo" did not match any module.
Warning: Selection "bar" did not match any object.
+ test_always_display clk -DEVENT_CLK
+ local subtest=clk
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v
...passed tests in tests/select
Passed techmap-dfflegalize_dlatch_const.ys
Passed opt-opt_share_bug2335.ys
Passed techmap-dfflegalize_sr_init.ys
Passed various-abc9.ys
Passed memory_bram test 04_03.
Passed techmap-pmux2mux.ys
Passed pp3-latches.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Running proc_rom.ys..
ERROR: Command stdout did have a line matching given regex "giraffe".
Expected error pattern 'stdout did have a line' found !!!
Passed various-deminout_unused.ys
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 0de35d2746, CPU: user 0.00s system 0.01s, MEM: 10.54 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 37% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ...
Passed techmap-techmap_chtype.ys
Passed ice40-bug1626.ys
Warning: wire '\d' is assigned in a block at <<EOT:7.10-7.20.
Warning: wire '\d' is assigned in a block at <<EOT:8.10-8.20.
Warning: wire '\d' is assigned in a block at <<EOT:9.10-9.20.
Warning: wire '\d' is assigned in a block at <<EOT:10.10-10.20.
Warning: wire '\d' is assigned in a block at <<EOT:11.10-11.20.
Warning: wire '\d' is assigned in a block at <<EOT:12.10-12.20.
Warning: wire '\d' is assigned in a block at <<EOT:13.10-13.20.
Warning: wire '\d' is assigned in a block at <<EOT:14.10-14.20.
Warning: wire '\d' is assigned in a block at <<EOT:15.10-15.20.
Warning: wire '\d' is assigned in a block at <<EOT:16.10-16.20.
Warning: wire '\d' is assigned in a block at <<EOT:17.10-17.20.
Warning: wire '\d' is assigned in a block at <<EOT:18.10-18.20.
Warning: wire '\d' is assigned in a block at <<EOT:19.10-19.20.
Warning: wire '\d' is assigned in a block at <<EOT:20.10-20.20.
Warning: wire '\d' is assigned in a block at <<EOT:21.10-21.20.
Warning: wire '\d' is assigned in a block at <<EOT:22.10-22.20.
Warning: wire '\d' is assigned in a block at <<EOT:25.3-25.9.
Passed verilog-delay_risefall.ys
Passed various-equiv_opt_multiclock.ys
Passed techmap-techmap_replace.ys
Passed various-exec.ys
+ ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Checking buffer.aag.

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v
Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed gowin-shifter.ys
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 11.64 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
Warning: wire '\d' is assigned in a block at <<EOT:20.13-20.23.
Warning: wire '\d' is assigned in a block at <<EOT:23.3-23.9.
+ diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v
Passed various-design2.ys
+ test_always_display clk_rst -DEVENT_CLK_RST
+ local subtest=clk_rst
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v
Passed opt-opt_share_bug2334.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed verilog-delay_mintypmax.ys
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' --

4. Executing Verilog backend.
Passed verilog-delay_time_scale.ys

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Passed xilinx-xilinx_srl.ys
Passed opt-opt_reduce_demux.ys
Dumping module `\m'.

End of script. Logfile hash: c95608ddf0, CPU: user 0.00s system 0.01s, MEM: 11.61 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 34% 2x opt_expr (0 sec), 23% 1x clean (0 sec), ...
Passed opt-opt_share_add_sub.ys
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v
Passed opt-opt_merge_basic.ys
Passed opt-opt_share_cat.ys
Passed opt-opt_share_bug2336.ys
Warning: wire '\d' is assigned in a block at <<EOT:7.7-7.17.
Warning: wire '\d' is assigned in a block at <<EOT:8.7-8.17.
Warning: wire '\d' is assigned in a block at <<EOT:9.7-9.17.
Warning: wire '\d' is assigned in a block at <<EOT:10.7-10.17.
Warning: wire '\d' is assigned in a block at <<EOT:11.7-11.17.
Warning: wire '\d' is assigned in a block at <<EOT:12.7-12.17.
Warning: wire '\d' is assigned in a block at <<EOT:13.7-13.17.
Warning: wire '\d' is assigned in a block at <<EOT:14.7-14.17.
Warning: wire '\d' is assigned in a block at <<EOT:15.7-15.17.
Warning: wire '\d' is assigned in a block at <<EOT:16.7-16.17.
Warning: wire '\d' is assigned in a block at <<EOT:17.8-17.18.
Warning: wire '\d' is assigned in a block at <<EOT:18.8-18.18.
Warning: wire '\d' is assigned in a block at <<EOT:19.8-19.18.

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v
Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Passed memory_bram test 00_01.
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 11.23 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 39% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v
+ test_always_display star -DEVENT_STAR
+ local subtest=star
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v
Running from the parent directory with temp/content2.dat
Checking cnt1.aag.

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_].
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-star-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Running from the parent directory with memfile/temp/content2.dat
Dumping module `\m'.

End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 11.60 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 37% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v
Warning: wire '\d' is assigned in a block at <<EOT:7.9-7.19.
Warning: wire '\d' is assigned in a block at <<EOT:8.9-8.19.
Warning: wire '\d' is assigned in a block at <<EOT:9.9-9.19.
Warning: wire '\d' is assigned in a block at <<EOT:10.9-10.19.
Warning: wire '\d' is assigned in a block at <<EOT:11.9-11.19.
Warning: wire '\d' is assigned in a block at <<EOT:12.9-12.19.
Warning: wire '\d' is assigned in a block at <<EOT:13.9-13.19.
Warning: wire '\d' is assigned in a block at <<EOT:14.9-14.19.
Warning: wire '\d' is assigned in a block at <<EOT:15.9-15.19.
Warning: wire '\d' is assigned in a block at <<EOT:16.9-16.19.
Warning: wire '\d' is assigned in a block at <<EOT:17.9-17.19.
Warning: wire '\d' is assigned in a block at <<EOT:18.9-18.19.
Warning: wire '\d' is assigned in a block at <<EOT:19.9-19.19.
Warning: wire '\d' is assigned in a block at <<EOT:20.9-20.19.
Warning: wire '\d' is assigned in a block at <<EOT:21.9-21.19.
Warning: wire '\d' is assigned in a block at <<EOT:22.9-22.19.
Passed techmap-dffunmap.ys
Running from the same directory with content1.dat

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v
Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed techmap-wireinit.ys
Running from the same directory with temp/content2.dat
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-star-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 11.57 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 36% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
+ diff yosys-always_display-star-1.v yosys-always_display-star-2.v
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
xprop_dffe_1npd: ok
Passed opt-opt_share_diff_port_widths.ys
Passed gatemate-logic.ys
+ test_always_display clk_en -DEVENT_CLK -DCOND_EN
+ local subtest=clk_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v
Running from a child directory with content1.dat
xprop_dffe_1npd: ok
Running rmdead.ys..
Passed techmap-dfflegalize_inv.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'.
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 12.03 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 43% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v
Running from a child directory with temp/content2.dat
Passed opt-opt_dff_srst.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v
Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 51e7fa3902, CPU: user 0.00s system 0.01s, MEM: 11.98 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 39% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v
Passed opt-opt_share_extend.ys
+ test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
+ local subtest=clk_rst_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).
...passed tests in tests/proc

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'.
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
<<EOT:4: ERROR: For loop variable declaration is missing initialization!
Expected error pattern 'For loop variable declaration is missing initialization!' found !!!
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Running from a child directory with content2.dat
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
<<EOT:3: ERROR: Cannot add memory `\x' because a signal with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add memory `\\x' because a signal with the same name was already created' found !!!
Dumping module `\m'.

End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.01s, MEM: 12.09 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 37% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ...
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_].
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v
Passed ice40-mul.ys
Passed verilog-conflict_memory_wire.ys
Checking a failure when zero length filename is provided

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v
Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed verilog-for_decl_no_init.ys

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.00s, MEM: 11.95 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 41% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ...
memory.v:15: ERROR: Can not open file `` for \$readmemb.
<<EOT:4: ERROR: For loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'For loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
+ diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v
Execution failed, which is OK.
Passed opt-memory_dff_trans.ys
Checking a failure when not existing filename is provided
Passed opt-opt_mem_priority.ys
+ test_always_display star_en -DEVENT_STAR -DCOND_EN
+ local subtest=star_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v
Passed various-func_port_implied_dir.ys
Passed intel_alm-counter.ys
Passed verilog-for_decl_no_sv.ys
memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb.
Execution failed, which is OK.
Passed techmap-dfflegalize_aldff.ys
...passed tests in tests/memfile
Passed various-fib_tern.ys
Passed opt-opt_share_bug2538.ys
Passed various-gen_if_null.ys
Passed opt-opt_expr_more.ys
Passed opt-opt_share_cat_multiuser.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Passed xilinx-bug3670.ys
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'.
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 11.96 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
Passed opt-opt_share_mux_tree.ys
Passed techmap-dfflegalize_adlatch_init.ys
Checking cnt1e.aag.
+ ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v
Passed verilog-doubleslash.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
     1/1: $write$yosys-always_display-star_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
Passed various-gzip_verilog.ys

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Warning: wire '\Q' is assigned in a block at <<EOT:6.9-6.15.
Warning: wire '\Q' is assigned in a block at <<EOT:8.9-8.15.
Warning: wire '\Q' is assigned in a block at <<EOT:10.9-10.15.
Warning: Resizing cell port top.inst2.a from 32 bits to 4 bits.
Warning: Resizing cell port top.inst1.a from 32 bits to 4 bits.
Passed verilog-for_decl_shadow.ys
Passed various-global_scope.ys
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' --

4. Executing Verilog backend.
Warning: Complex async reset for dff `\Q'.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Passed various-hierarchy_defer.ys
Dumping module `\m'.

End of script. Logfile hash: 18895a2046, CPU: user 0.01s system 0.01s, MEM: 12.04 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 41% 2x opt_expr (0 sec), 16% 1x clean (0 sec), ...
Passed various-help.ys
Passed verilog-func_arg_mismatch_3.ys
+ diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v
Passed verilog-func_arg_mismatch_1.ys
+ test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=
+ local subtest=dec_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v
Passed pp3-mux.ys
Passed various-design.ys
Passed techmap-recursive_runtest.sh
Passed various-hierarchy_generate.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0
<<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
Passed xilinx-opt_lut_ins.ys
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0
Checking empty.aag.
Passed opt-opt_dff_en.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
<<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected' found !!!
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0
Warning: Wire top.\t is used but has no driver.
Warning: Wire top.\in is used but has no driver.
Passed opt-opt_share_large_pmux_part.ys
Dumping module `\m'.

End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.01s, MEM: 11.27 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 22% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
Passed various-integer_real_bad_syntax.ys
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v
Passed verilog-func_arg_mismatch_4.ys
Passed various-integer_range_bad_syntax.ys
Passed verilog-func_arg_mismatch_2.ys
Passed techmap-dfflibmap_formal.ys
Passed techmap-dfflegalize_adff_init.ys
Testing on dff.lib..

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed various-hierarchy_param.ys
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Passed verilog-func_typename_ret.ys
Dumping module `\m'.

End of script. Logfile hash: 4be9539e85, CPU: user 0.01s system 0.00s, MEM: 11.56 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 22% 1x clean (0 sec), 18% 2x read_verilog (0 sec), ...
+ diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v
Passed opt-opt_reduce_bmux.ys
Passed verilog-func_task_arg_copying.ys
Passed ice40-shifter.ys
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v
Passed opt-opt_share_large_pmux_cat.ys
attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
Passed verilog-genblk_case.ys
Passed opt-opt_dff_const.ys
Passed various-json_escape_chars.ys
Passed ice40-tribuf.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
<<EOT:4: ERROR: Cannot declare module port `\x' within a generate block.
Expected error pattern 'Cannot declare module port `\\x' within a generate block\.' found !!!
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_].
+ ./iverilog-roundtrip-dec_unsigned
Passed verilog-gen_block_end_label_only.ys
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v
...passed tests in tests/rpc
Passed various-keep_hierarchy.ys
ERROR: Identifier `\b' is implicitly declared.
Expected error pattern 'is implicitly declared.' found !!!
Passed intel_alm-adffs.ys
Passed verilog-genblk_port_decl.ys
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Passed various-logger_nowarning.ys
Passed ecp5-fsm.ys
Warning: Resizing cell port top.u3.out from 1 bits to 2 bits.
Passed verilog-func_tern_hint.ys
<<EOT:2: ERROR: Generate for loop variable declaration is missing initialization!
Expected error pattern 'Generate for loop variable declaration is missing initialization!' found !!!
Passed various-logger_error.ys
Passed verilog-gen_block_end_label_wrong.ys
<<EOT:2: ERROR: Generate for loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'Generate for loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed opt-opt_share_large_pmux_cat_multipart.ys
<<EOF:0: ERROR: Can't find object for defparam `$1`!
Expected error pattern 'Can't find object for defparam' found !!!
Passed verilog-genfor_decl_no_init.ys
Passed various-logger_warning.ys
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21.
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21.
Passed verilog-global_parameter.ys
Passed techmap-dfflegalize_dlatchsr_init.ys
Passed verilog-genfor_decl_no_sv.ys
+ ./iverilog-roundtrip-dec_unsigned-1
Passed verilog-genvar_loop_decl_2.ys
Passed memory_bram test 00_02.
Warning: No SAT model available for cell $auto$rename.cc:467:execute$62_gold (bb).
Warning: No SAT model available for cell $auto$rename.cc:467:execute$63_gold (bb).
Warning: No SAT model available for cell $auto$rename.cc:467:execute$64_gold (bb).
Checking false.aag.
Passed verilog-genvar_loop_decl_3.ys
Passed verilog-genvar_loop_decl_1.ys
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v
Warning: Resizing cell port top.inst.i from 32 bits to 4 bits.
Passed ice40-bug1598.ys
Passed various-json_scopeinfo.ys
<<EOT:7: ERROR: Identifier `\y' is implicitly declared and `default_nettype is set to none.
Expected error pattern 'Identifier `\\y' is implicitly declared and `default_nettype is set to none' found !!!
Passed verilog-hidden_decl.ys
ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!!
Passed various-fib.ys
+ ./iverilog-roundtrip-dec_unsigned-1
Passed intel_alm-mux.ys
Passed various-lcov.ys
Passed verilog-macro_arg_tromp.ys
Warning: Found log message matching -W regex:
Added regex 'Successfully finished Verilog frontend.' to expected warning messages list.
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Warning: Found log message matching -W regex:
Successfully finished Verilog frontend.
Passed verilog-macro_unapplied_newline.ys
+ diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log
+ diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log
ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!!
Passed verilog-ifdef_nest.ys
Passed opt-opt_share_large_pmux_multipart.ys
Passed pp3-adffs.ys
Passed techmap-shiftx2mux.ys
+ test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed
+ local subtest=dec_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v
Passed verilog-macro_unapplied.ys
Passed verilog-net_types.ys
Passed gowin-fsm.ys
Passed various-logger_warn.ys
<<EOF:3: ERROR: Module name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Module name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
<<EOF:3: ERROR: Package name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Package name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Dumping module `\m'.

End of script. Logfile hash: bbdfa5ca92, CPU: user 0.00s system 0.01s, MEM: 11.64 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 23% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v
Passed verilog-module_end_label.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v
Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Passed verilog-package_end_label.ys
xprop_shiftx_4u2s_8: ok
Passed verilog-include_self.ys
xprop_shiftx_4u2s_8: ok

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
<<EOF:3: ERROR: Parameter defaults can only be omitted in SystemVerilog mode!
Expected error pattern 'Parameter defaults can only be omitted in SystemVerilog mode!' found !!!
Dumping module `\m'.

End of script. Logfile hash: b233de92a6, CPU: user 0.01s system 0.01s, MEM: 12.00 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 22% 1x opt_expr (0 sec), 22% 2x read_verilog (0 sec), ...
+ diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v
Passed various-logic_param_simple.ys
Passed various-mem2reg.ys
Passed machxo2-logic.ys
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v
<<EOF:3: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed verilog-param_no_default_not_svmode.ys
Testing on idranges.lib..
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed verilog-param_default.ys
+ ./iverilog-roundtrip-dec_signed
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v
Passed verilog-localparam_no_default_1.ys
Checking halfadder.aag.
Passed anlogic-dffs.ys
Passed verilog-package_task_func.ys
ERROR: Unterminated preprocessor conditional!
Expected error pattern 'Unterminated preprocessor conditional!' found !!!
Passed verilog-incdec.ys
Passed verilog-param_int_types.ys
Passed verilog-ifdef_unterminated.ys
Passed verilog-param_no_default_unbound_1.ys
Passed memory_bram test 03_02.
Passed opt-opt_hier.tcl
+ ./iverilog-roundtrip-dec_signed-1
Passed opt-opt_dff_mux.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v
Passed verilog-parameters_across_files.ys
Passed ice40-logic.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed verilog-param_no_default_unbound_5.ys
Passed various-param_struct.ys
Passed verilog-param_no_default_unbound_2.ys
Passed techmap-zinit.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/simcells.v:476)
Passed qlf_k6n10f-add_sub.ys
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
+ ./iverilog-roundtrip-dec_signed-1
Passed verilog-param_no_default_unbound_4.ys
+ diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log
Passed ecp5-tribuf.ys
Passed various-reg_wire_error.ys
+ diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log
+ test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=
+ local subtest=hex_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v
Passed various-primitives.ys
Passed various-printattr.ys
Passed various-rename_scramble_name.ys
Checking inverter.aag.
Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
Passed anlogic-fsm.ys
<<EOF:2: ERROR: Parameter `\Y' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\Y' has no default value and has not been overridden!' found !!!

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Passed verilog-param_no_default_unbound_3.ys
Dumping module `\m'.

End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 11.57 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v
Passed various-rand_const.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed pp3-fsm.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/quicklogic/pp3'
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.
...passed tests in tests/arch/quicklogic/pp3

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 11.57 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 22% 1x opt_expr (0 sec), 22% 1x clean (0 sec), ...
+ diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v
Test: case_expr_query -> ok
Passed memory_bram test 04_01.
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v
Passed various-const_func.ys
Passed various-scratchpad.ys
Passed various-memory_word_as_index.ys
Testing on issue3498_bad.lib..
Passed various-rtlil_signed_attribute.ys
Passed various-peepopt_formal.ys
+ ./iverilog-roundtrip-hex_unsigned
Passed techmap-kogge-stone.tcl
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v
Passed various-rename_unescape.ys
Passed various-rtlil_z_bits.ys
Passed various-scopeinfo.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_].
Checking notcnt1.aag.
Passed techmap-abc9.ys
Passed various-script.ys
{
  "creator": "Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)",
  "modules": {
    "top": {
      "attributes": {
        "keep": "00000000000000000000000000000001",
        "top": "00000000000000000000000000000001",
        "src": "setundef.sv:5.1-10.10"
      },
      "ports": {
        "o": {
          "direction": "output",
          "bits": [ "0", "0" ]
        }
      },
      "cells": {
        "$assert$setundef.sv:8$2": {
          "hide_name": 1,
          "type": "$assert",
          "parameters": {
          },
          "attributes": {
            "src": "setundef.sv:8.3-8.21"
          },
          "port_directions": {
            "A": "input",
            "EN": "input"
          },
          "connections": {
            "A": [ "1" ],
            "EN": [ "1" ]
          }
        },
        "$auto$chformal.cc:428:execute$6": {
          "hide_name": 1,
          "type": "$not",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ "1" ],
            "Y": [ 2 ]
          }
        },
        "$auto$chformal.cc:430:execute$8": {
          "hide_name": 1,
          "type": "$and",
          "parameters": {
            "A_SIGNED": "00000000000000000000000000000000",
            "A_WIDTH": "00000000000000000000000000000001",
            "B_SIGNED": "00000000000000000000000000000000",
            "B_WIDTH": "00000000000000000000000000000001",
            "Y_WIDTH": "00000000000000000000000000000001"
          },
          "attributes": {
          },
          "port_directions": {
            "A": "input",
            "B": "input",
            "Y": "output"
          },
          "connections": {
            "A": [ 2 ],
            "B": [ "1" ],
            "Y": [ 3 ]
          }
        },
        "foo": {
          "hide_name": 0,
          "type": "$scopeinfo",
          "parameters": {
            "TYPE": "module"
          },
          "attributes": {
            "cell_module_not_derived": "00000000000000000000000000000001",
            "cell_src": "setundef.sv:6.15-6.21",
            "module": "$paramod\\foo\\a=2'00",
            "module_hdlname": "foo",
            "module_src": "setundef.sv:1.1-3.10"
          },
          "port_directions": {
          },
          "connections": {
          }
        }
      },
      "netnames": {
        "$assert$setundef.sv:8$2_EN": {
          "hide_name": 1,
          "bits": [ "1" ],
          "attributes": {
            "src": "setundef.sv:8.3-8.21"
          }
        },
        "$auto$rtlil.cc:2957:Not$7": {
          "hide_name": 1,
          "bits": [ 2 ],
          "attributes": {
          }
        },
        "$auto$rtlil.cc:3004:And$9": {
          "hide_name": 1,
          "bits": [ 3 ],
          "attributes": {
          }
        },
        "$eq$setundef.sv:8$3_Y": {
          "hide_name": 1,
          "bits": [ "1" ],
          "attributes": {
            "src": "setundef.sv:8.10-8.20"
          }
        },
        "foo.o": {
          "hide_name": 0,
          "bits": [ "0", "0" ],
          "attributes": {
            "hdlname": "foo o",
            "src": "setundef.sv:1.47-1.48"
          }
        },
        "o": {
          "hide_name": 0,
          "bits": [ "0", "0" ],
          "attributes": {
            "src": "setundef.sv:5.25-5.26"
          }
        }
      }
    }
  }
}
Test: arrays02 -> ok
Passed various-setundef.ys
Passed ecp5-rom.ys
Passed verilog-int_types.ys
Passed ecp5-shifter.ys
Passed ice40-spram.ys
Passed various-pmux2shiftx.ys
Passed techmap-sklansky.tcl
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Passed verilog-param_no_default.ys
+ ./iverilog-roundtrip-hex_unsigned-1
Passed verilog-past_signedness.ys
Passed verilog-port_int_types.ys
Test: code_hdl_models_d_latch_gates -> ok
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_].
Passed ice40-bug1597.ys
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v
<<EOF:2: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
Passed various-sformatf.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Passed verilog-localparam_no_default_2.ys
Warning: Module top contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers.
Passed verilog-prefix.ys
+ ./iverilog-roundtrip-hex_unsigned-1
Passed various-signext.ys
Passed various-port_sign_extend.ys
+ diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log
Passed various-signed.ys
+ diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log
Checking notcnt1e.aag.
+ test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed
+ local subtest=hex_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v
Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
<<EOF:2: Warning: octal escape exceeds \377

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Test: unnamed_block_decl -> ok
<<EOF:2: Warning: '?' not a valid digit in octal escape sequence.
<<EOF:2: Warning: 'X' not a valid digit in hex escape sequence.
<<EOF:2: Warning: ignoring invalid hex escape.
Optimizing module m.
<<EOF:3: Warning: Multi-line string literals should be triple-quoted or escaped.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 824c3b1e65, CPU: user 0.01s system 0.00s, MEM: 11.69 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v
Test: always01 -> ok
Passed various-splitnets.ys
Passed machxo2-tribuf.ys
Passed various-sim_const.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v
Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Passed various-src.ys
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Passed verilog-sbvector.ys
Passed various-peepopt.ys
Dumping module `\m'.

End of script. Logfile hash: f18b3fa15b, CPU: user 0.00s system 0.01s, MEM: 11.60 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 24% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v
Passed verilog-sign_array_query.ys
+ ./iverilog-roundtrip-hex_signed
Passed verilog-string-literals.ys
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v
<<EOT:6: ERROR: syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT
Expected error pattern 'syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT' found !!!
Passed verilog-typedef_across_files.ys
+ ./iverilog-roundtrip-hex_signed-1
Passed verilog-task_attr.ys
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
Testing on non-ascii.lib..
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v
Passed various-shregmap.ys
Passed memory_bram test 04_00.
Passed verilog-typedef_const_shadow.ys
Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits.
+ ./iverilog-roundtrip-hex_signed-1
Passed various-stat.ys
Passed verilog-typedef_legacy_conflict.ys
Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits.
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:41)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:86)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:87)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:17)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:21)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:25)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:30)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:34)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:38)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2153)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2154)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2155)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2156)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2157)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2158)
+ diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log
+ diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log
+ test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=
+ local subtest=oct_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.01s, MEM: 11.64 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 23% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
Test: code_hdl_models_half_adder_gates -> ok
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2925)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2926)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2988)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2989)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:2990)
Warning: Critical-path does not terminate in a recognised endpoint.
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:3203)
Warning: Yosys has only limited support for tri-state logic at the moment. (/usr/local/google/home/cannada/Software/yosys/yosys/share/ice40/cells_sim.v:3210)
Warning: Cell type 'const0' not recognised! Ignoring.
Passed verilog-size_cast.ys
Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Passed various-sta.ys
Passed verilog-roundtrip_proc.ys
Passed various-submod.ys
Passed various-submod_extract.ys
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
ERROR: Duplicate macro arguments with name `x'.
Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
Dumping module `\m'.

End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.01s, MEM: 11.67 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 22% 1x opt_expr (0 sec), 21% 1x clean (0 sec), ...
+ diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v
[1]ERROR: Mismatched brackets in macro argument: [ and }.
Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
Passed verilog-unique_if_else_begin.ys
ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!!
Passed various-sv_defines_dup.ys
Passed various-sv_defines_mismatch.ys
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v
Passed microchip-dff_opt.ys
Passed various-sv_defines_too_few.ys
Passed various-struct_access.ys
Passed verilog-unbased_unsized_shift.ys
[2]+ ./iverilog-roundtrip-oct_unsigned
Passed verilog-unbased_unsized.ys
Warning: No SAT model available for cell B_0 ($specrule).
Warning: No SAT model available for cell C_0 ($specrule).
Warning: No SAT model available for cell A_0 ($specify3).
Passed various-tcl_apis.ys
[3]Warning: No SAT model available for cell A_0 ($specify2).
Warning: No SAT model available for cell B_0 ($specify2).
Test: case_expr_extend -> ok
Test: case_expr_const -> ok
Passed various-wrapcell.ys
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v
Testing on normal.lib..
Passed various-specify.ys
Passed various-wreduce2.ys
Test: genblk_port_shadow -> ok
<<EOF:5: ERROR: unique keyword cannot be used for 'else if' branch.
Expected error pattern 'unique keyword cannot be used for 'else if' branch' found !!!
Checking or_.aag.
+ ./iverilog-roundtrip-oct_unsigned-1
Test: local_loop_var -> ok
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v
[4]Warning: Wire adff.q has an unprocessed 'init' attribute.
Passed verilog-unique_if_else.ys
Passed ecp5-latches.ys
Passed various-sv_defines.ys
+ ./iverilog-roundtrip-oct_unsigned-1
+ diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log
+ diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log
Test: code_hdl_models_clk_div -> ok
+ test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed
+ local subtest=oct_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v
Passed verilog-priority_if_enc.ys
Passed verilog-unique_if.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Passed ice40-fsm.ys
Dumping module `\m'.

End of script. Logfile hash: 7ec82b15e3, CPU: user 0.01s system 0.00s, MEM: 11.54 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 24% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v
Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: a747b9bd4f, CPU: user 0.01s system 0.00s, MEM: 11.61 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v
Test: code_hdl_models_encoder_4to2_gates -> ok
Passed ice40-latches.ys
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v
Passed various-wreduce.ys
ERROR: Found `elsif outside of macro conditional branch!
Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!!
Passed machxo2-mux.ys
ERROR: Found `else outside of macro conditional branch!
Expected error pattern 'Found `else outside of macro conditional branch!' found !!!
Test: implicit_en -> ok
Passed various-xaiger.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Test: shared_ports -> ok
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed verilog-unmatched_elsif.ys
Passed verilog-unmatched_else.ys
Passed verilog-unmatched_endif.ys
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0
+ ./iverilog-roundtrip-oct_signed
Test: code_hdl_models_d_ff_gates -> ok
svinterface1_tb.v:50: $finish called at 420000 (10ps)
Passed verilog-unmatched_endif_2.ys
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v
Passed verilog-unique_priority_case.ys
Passed ecp5-logic.ys
Passed opt-opt_lut.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_].
+ ./iverilog-roundtrip-oct_signed-1
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_].
Test: no_implicit_en -> ok
svinterface1_tb.v:50: $finish called at 420000 (10ps)
<<EOT:3: ERROR: Local declaration in unnamed block is only supported in SystemVerilog mode!
Expected error pattern 'Local declaration in unnamed block is only supported in SystemVerilog mode!' found !!!
Test: simple_sram_byte_en -> ok
Passed verilog-unique0_if_enc.ys
Passed verilog-unnamed_genblk.ys
Passed techmap-han-carlson.tcl
Passed various-write_gzip.ys
ok
Test: code_hdl_models_decoder_using_assign -> ok
Passed verilog-unnamed_block.ys
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v
Warning: Complex async reset for dff `\Q'.
Passed verilog-unique_priority_if.ys
Passed techmap-dfflegalize_dffsr_init.ys
Test: svinterface_at_top -> Passed verilog-unreachable_case_sign.ys
+ ./iverilog-roundtrip-oct_signed-1
[5]Passed various-formalff_declockgate.ys
+ diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log
Test: implicit_ports -> ok
Test: memwr_port_connection -> ok
+ diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log
Passed intel_alm-mul.ys
Test: test_simulation_buffer -> ok
Passed opt-opt_rmdff.ys
+ test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=
+ local subtest=bin_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v
Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51.
Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66.
Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90.
Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81.
Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91.

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Passed memory_bram test 01_04.
Warning: wire '\b' is assigned in a block at <<EOF:2.38-2.43.
Warning: wire '\b' is assigned in a block at <<EOF:3.42-3.48.
Warning: wire '\b' is assigned in a block at <<EOF:12.29-12.34.
Warning: wire '\b' is assigned in a block at <<EOF:13.33-13.39.
Warning: wire '\b' is assigned in a block at <<EOF:23.9-23.14.
Warning: wire '\b' is assigned in a block at <<EOF:24.9-24.15.
Warning: wire '\b' is assigned in a block at <<EOF:25.9-25.15.
Test: code_hdl_models_mux_using_case -> ok
Test: ifdef_1 -> ok
Passed machxo2-dffs.ys
Passed verilog-upto.ys
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.
[6]Passed verilog-wire_and_var.ys

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Test: attrib01_module -> ok
Checking symbols.aag.
Dumping module `\m'.

End of script. Logfile hash: 270b564880, CPU: user 0.00s system 0.01s, MEM: 11.66 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 23% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: dc9f56cb10, CPU: user 0.00s system 0.01s, MEM: 12.06 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 23% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v
Passed verilog-struct_access.ys
+ ./iverilog-roundtrip-bin_unsigned
Test: code_hdl_models_decoder_using_case -> ok
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v
[7]Test: code_hdl_models_encoder_using_case -> ok
Test: always03 -> ok
Passed ecp5-counter.ys
Test: test_simulation_seq -> ok
Passed verilog-unique_if_enc.ys
Test: ifdef_2 -> ok
Passed machxo2-fsm.ys
+ ./iverilog-roundtrip-bin_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v
Checking toggle.aag.
Test: arraycells -> ok
+ ./iverilog-roundtrip-bin_unsigned-1
Test: aes_kexp128 -> ok
Passed various-logger_cmd_error.sh
Test: forgen01 -> ok
Test: code_hdl_models_mux_using_assign -> ok
Passed verilog-void_func.ys
+ diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log
[8]+ diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log
+ test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed
+ local subtest=bin_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v
Passed various-clk2fflogic_effects.sh
Passed ice40-dffs.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
[9]Testing on processdefs.lib..
Test: always01 -> ok
Passed intel_alm-fsm.ys
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Test: attrib08_mod_inst -> ok
Passed verilog-mem_bounds.ys
Passed ecp5-bug2409.ys
Test: wide_thru_priority -> ok
Passed various-hierarchy.sh
Test: code_hdl_models_parity_using_bitwise -> ok
Test: code_hdl_models_parallel_crc -> ok
[10]Passed verilog-unbased_unsized_tern.ys
Test: matching_end_labels -> ok
Test: code_hdl_models_lfsr_updown -> ok
[11]Passed various-chparam.sh
Checking toggle-re.aag.
Dumping module `\m'.

End of script. Logfile hash: 7709253822, CPU: user 0.00s system 0.01s, MEM: 11.60 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v
Test: code_tidbits_wire_example -> ok
Passed ecp5-dffs.ys
Test: arrays01 -> ok

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v
Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Test: code_verilog_tutorial_simple_if -> ok
Passed various-plugin.sh
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 11.66 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 23% 1x clean (0 sec), 19% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v
Test: attrib04_net_var -> ok
Passed microchip-uram_sr.ys
+ ./iverilog-roundtrip-bin_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v
Test: genblk_collide -> ok
Test: carryadd -> ok
+ ./iverilog-roundtrip-bin_signed-1
Passed various-muxpack.ys
Test: code_hdl_models_pri_encoder_using_assign -> ok
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v
Passed gowin-dffs.ys
Test: carryadd -> ok
[12]Checking true.aag.
Test: case_expr_const -> ok
Test: forgen02 -> ok
+ ./iverilog-roundtrip-bin_signed-1
Passed anlogic-mux.ys
+ diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log
+ diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log
+ test_cxxrtl always_full
+ local subtest=always_full
+ shift
+ ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc'
Test: wide_read_sync -> ok

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' --

1. Executing Verilog-2005 frontend: always_full.v
Test: case_expr_non_const -> ok
Test: always02 -> ok
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
Passed techmap-cmp2lcu.ys

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
Test: code_hdl_models_tff_sync_reset -> ok
Removed 0 unused cells and 207 unused wires.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
root of   0 design levels: always_full         
Automatically selected always_full as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \always_full

3.1.3. Analyzing design hierarchy..
Top module:  \always_full
Removed 0 unused modules.
Module always_full directly or indirectly displays text -> setting "keep" attribute.

3.2. Executing FLATTEN pass (flatten design).

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

<suppressed ~12 debug messages>

End of script. Logfile hash: af8795c7c4, CPU: user 0.01s system 0.01s, MEM: 13.49 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 26% 2x read_verilog (0 sec), 24% 2x write_cxxrtl (0 sec), ...
Test: genblk_collide -> ok
[13]Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Passed microchip-uram_ar.ys
[14]Passed various-logger_fail.sh
+ gcc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++
+ ./cxxrtl-test-value_fuzz
Passed various-async.sh
Test: test_simulation_nor -> ok
Passed various-svalways.sh
Test: const_fold_func -> ok
Test: attrib09_case -> ok
[15]Test: firrtl_938 -> ok
Test: localparam_attr -> ok
[16]Test: code_verilog_tutorial_if_else -> ok
Test: always02 -> ok
Passed techmap-dfflegalize_dff_init.ys
Test: code_hdl_models_parity_using_function -> ok
Test: read_two_mux -> ok
Testing on semicolextra.lib..
Test: attrib08_mod_inst -> ok
Checking and_.aig.
[17]Passed various-sv_implicit_ports.sh
Test: code_hdl_models_dff_sync_reset -> ok
Test: nested_genblk_resolve -> ok
Test: attrib03_parameter -> ok
Test: test_simulation_nand -> ok
Test: lesser_size_cast -> ok
Test: aes_kexp128 -> ok
Test: code_hdl_models_up_counter -> ok
Checking and_to_bad_out.aig.
Test: loop_var_shadow -> ok
Test: macros -> ok
Test: code_tidbits_reg_seq_example -> ok
Passed ecp5-dpram.ys
[18]Test: attrib02_port_decl -> ok
Test: param_attr -> ok
Test: code_hdl_models_mux_using_if -> ok
Test: case_expr_non_const -> ok
Test: specify -> ok
Test: code_hdl_models_clk_div_45 -> ok
Test: test_simulation_and -> ok
Test: attrib04_net_var -> ok
Test: code_hdl_models_serial_crc -> ok
Test: code_verilog_tutorial_n_out_primitive -> ok
Test: nested_genblk_resolve -> ok
Test: const_branch_finish -> ok
Test: code_hdl_models_GrayCounter -> ok
Passed techmap-mem_simple_4x1_runtest.sh
Test: test_simulation_vlib -> ok
Test: test_simulation_or -> ok
Test: code_tidbits_fsm_using_always -> ok
Test: code_verilog_tutorial_simple_function -> ok
Test: code_verilog_tutorial_v2k_reg -> ok
Test: code_hdl_models_one_hot_cnt -> ok
Test: code_hdl_models_full_adder_gates -> ok
Test: forloops -> ok
Test: code_verilog_tutorial_task_global -> ok
xprop_or_2u2_2: ok
Test: code_hdl_models_full_subtracter_gates -> ok
xprop_or_2u2_2: ok
[19]Test: code_hdl_models_arbiter -> ok
Test: code_hdl_models_gray_counter -> ok
Test: attrib06_operator_suffix -> ok
Test: code_hdl_models_lfsr -> ok
xprop_and_1s1_2: ok
Test: case_expr_extend -> ok
xprop_and_1s1_2: ok
Test: read_arst -> ok
Test: wide_read_trans -> ok
Test: code_hdl_models_decoder_2to4_gates -> ok
Checking buffer.aig.
Test: code_hdl_models_mux_2to1_gates -> ok
Test: attrib03_parameter -> ok
Passed anlogic-latches.ys
Test: fiedler-cooley -> ok
Test: func_recurse -> ok
Test: attrib02_port_decl -> ok
Test: forloops -> ok
Test: dff_init -> ok
Checking cnt1.aig.
Passed memory_bram test 04_02.
Test: test_simulation_inc -> ok
Passed gatemate-fsm.ys
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Test: loop_prefix_case -> ok
Test: attrib09_case -> ok
Test: code_verilog_tutorial_escape_id -> ok
Test: code_tidbits_asyn_reset -> ok
Test: code_tidbits_blocking -> ok
Test: graphtest -> ok
Passed gatemate-dffs.ys
Test: wide_write -> ok
Test: genblk_order -> ok
Testing on semicolmissing.lib..
Test: hierdefparam -> ok
Test: code_verilog_tutorial_always_example -> ok
Checking cnt1e.aig.
Passed ice40-rom.ys
Test: fiedler-cooley -> ok
Test: code_verilog_tutorial_which_clock -> ok
xprop_and_1u1_1: ok
xprop_and_1u1_1: ok
[20]Test: code_verilog_tutorial_bus_con -> ok
Test: code_hdl_models_parity_using_assign -> ok
Checking empty.aig.
Passed gatemate-counter.ys
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
[21]Passed nanoxplore-fsm.ys
[1]Test: retime -> ok
Test: ifdef_1 -> ok
Test: code_hdl_models_encoder_using_if -> ok
[2]Test: wide_read_async -> ok
Test: defvalue -> ok
Test: code_hdl_models_dff_async_reset -> ok
Test: matching_end_labels -> ok
Test: ifdef_2 -> ok
Test: arrays02 -> ok
Test: code_tidbits_nonblocking -> ok
[3]Test: named_genblk -> ok
[4][5][8][7][6]Test: code_hdl_models_up_counter_load -> ok
[9][10]Test: forgen01 -> ok
Test: case_expr_query -> ok
xprop_xor_1s1_2: ok
[11][12]xprop_xor_1s1_2: ok
Checking false.aig.
Test: loop_var_shadow -> ok
Test: graphtest -> ok
Test: attrib06_operator_suffix -> ok
Test: string_format -> ok
[13][22][14]Test: code_hdl_models_tff_async_reset -> ok
[16][15]Test: arrays03 -> ok
Test: string_format -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: trans_addr_enable -> ok
[23]Test: test_simulation_xor -> ok
Test: code_verilog_tutorial_addbit -> ok
[17]Test: genblk_dive -> ok
[18]Test: const_branch_finish -> ok
xprop_xor_1u1_1: ok
Test: macro_arg_surrounding_spaces -> ok
xprop_xor_1u1_1: ok
Test: test_simulation_xnor -> ok
Test: const_fold_func -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_verilog_tutorial_multiply -> ok
Test: module_scope_case -> ok
Passed nanoxplore-tribuf.ys
[19]Passed opt-opt_mem_feedback.ys
[20]Test: code_verilog_tutorial_parity -> ok
[24]Test: genblk_port_shadow -> ok
[21]Test: code_tidbits_syn_reset -> ok
Test: code_verilog_tutorial_decoder -> ok
[22]svinterface_at_top_tb.v:61: $finish called at 420000 (10ps)
Test: code_verilog_tutorial_parallel_if -> ok
xprop_or_1u1_1: ok
Test: arrays01 -> ok
[23][24]Test: memwr_port_connection -> ok
xprop_or_1u1_1: ok
[26][27][25][28][29]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
[34][35][33]Test: retime -> ok
xprop_reduce_bool_1u_1: ok
xprop_reduce_bool_1u_1: ok
[36][25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_verilog_tutorial_d_ff -> ok
xprop_and_2u2_2: ok
xprop_and_2u2_2: ok
Test: code_verilog_tutorial_flip_flop -> ok
[37][38]xprop_or_1s1_2: ok
xprop_or_1s1_2: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: constpower -> ok
Test: test_parser -> ok
Test: trans_sp -> ok
Passed ice40-ice40_opt.ys
Test: verilog_primitives -> ok
[40][39]Test: constpower -> ok
Test: process -> ok
[41]Test: t_init_lut_zeros_any -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: t_init_lut_val_no_undef -> ok
[43][42][44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_logic_not_3u_3: ok
[30]xprop_xnor_2u2_2: ok
xprop_logic_not_3u_3: ok
xprop_xnor_2u2_2: ok
[46][45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_verilog_tutorial_mux_21 -> ok
Test: const_func_shadow -> ok
Passed qlf_k6n10f-logic.ys
[47]Test: module_scope_case -> ok
[26]Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps)
[48][49]xprop_xnor_1u1_1: ok
Test: t_sync_small_block -> ok
xprop_xnor_1u1_1: ok
[32]Testing on XNOR2X1.lib..
Test: issue00710 -> ok
Test: unnamed_block_decl -> ok
Test: dff_init -> ok
[31]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_logic_and_3u3_3: ok
Test: attrib01_module -> ok
Test: loop_prefix_case -> ok
ERROR!
Test: always03 -> ok
Test: t_init_lut_x_no_undef -> ok
Test: t_mixed_36_9 -> ok
Test: t_init_lut_val2_no_undef -> ok
Test: module_scope_func -> ok
xprop_logic_and_3u3_3: ok
Test: load_and_derive ->xprop_gt_5u3_2: ok
xprop_gt_5u3_2: ok
Test: func_width_scope -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: t_sync_small -> ok
Test: t_ram_18b2B -> ok
Test: code_hdl_models_rom_using_case -> ok
Test: hierarchy -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_ge_5s3_2: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
[27]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_ge_5s3_2: ok
Test: macro_arg_surrounding_spaces -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_tidbits_fsm_using_single_always -> ok
Test: code_tidbits_reg_combo_example -> ok
Test: usb_phy_tests -> ok
ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
KWarning: Wire my_dffe.q has an unprocessed 'init' attribute.
Test: resolve_types ->Checking halfadder.aig.
Test: t_ram_9b1B -> ok
Test: fsm -> ok
Test: undef_eqx_nex -> ok
Test: code_verilog_tutorial_tri_buf -> ok
Test: named_genblk -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: t_clock_a4_wANYrANYsFalse -> ok
xprop_logic_not_3s_1: ok
xprop_logic_not_3s_1: ok
xprop_reduce_xor_3u_3: ok
Test: t_init_lut_val_any -> ok
Kxprop_reduce_xor_3u_3: ok
KTest: wide_read_mixed -> ok
Test: func_block -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: module_scope_func -> ok
xprop_xor_2u2_2: ok
xprop_xor_2u2_2: ok
Test: signedexpr -> ok
Test: arraycells -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
[28]Test: t_clock_a4_wANYrANYsTrue -> ok
Test: t_clock_a4_wANYrPOSsFalse -> ok
Test: const_func_shadow -> ok
Test: t_init_lut_x_any -> ok
Warning: Complex async reset for dff `\Q'.
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_reduce_bool_3s_3: ok
ok
Test: signed_full_slice -> ok
xprop_reduce_bool_3s_3: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: lesser_size_cast -> ok
xprop_reduce_xnor_3u_3: ok
...passed tests in tests/svinterfaces
xprop_reduce_xnor_3u_3: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_tidbits_fsm_using_function -> ok
Checking inverter.aig.
Test: sign_part_assign -> ok
Passed opt-opt_dff_sr.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/opt'
Test: param_attr -> ok
...passed tests in tests/opt
Test: t_init_9b1B_val_no_undef -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: func_recurse -> ok
Test: genblk_order -> ok
[29]Passed qlf_k6n10f-counter.ys
xprop_reduce_or_3s_3: ok
xprop_reduce_or_3s_3: ok
xprop_logic_or_1u1_1: ok
K[30]xprop_logic_or_1u1_1: ok
Test: mem2reg_bounds_tern -> ok
Test: usb_phy_tests -> ok
Passed memory_bram test 03_00.
Test: t_clock_a4_wPOSrPOSsFalse -> ok
[31]Test: t_init_lut_val_zero -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: code_verilog_tutorial_good_code -> ok
Test: hierarchy -> ok
Test: t_init_lut_val2_any -> ok
Test: t_clock_a4_wNEGrANYsFalse -> ok
Test: amber23_sram_byte_en -> ok
Test: t_init_lut_x_zero -> ok
Test: code_verilog_tutorial_first_counter -> ok
[32]xprop_sshl_4s3u_3: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_lt_5s3_2: ok
xprop_xnor_1s1_2: ok
xprop_logic_or_3s3_1: ok
xprop_sshl_4s3u_3: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: forgen02 -> ok
Running libcache.ys..
xprop_logic_or_3s3_1: ok
xprop_xnor_1s1_2: ok
xprop_lt_5s3_2: ok
Test: genblk_dive -> ok
xprop_reduce_xor_3s_3: ok
Test: macro_arg_spaces -> ok
Test: verilog_primitives -> ok
xprop_reduce_xor_3s_3: ok
Passed nanoxplore-shifter.ys
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
[33]xprop_sub_5u3_3: ok
Kxprop_sub_5u3_3: ok
xprop_pos_3s_5: ok
xprop_pos_3s_5: ok
Running options_test.ys..
xprop_eq_5u3_2: ok
Test: localparam_attr -> ok
Test: t_async_small_block -> ok
Passed qlf_k6n10f-dffs.ys
xprop_eq_5u3_2: ok
xprop_lt_5u3_2: ok
xprop_shl_4s3u_3: ok
xprop_lt_5u3_2: ok
[34]xprop_shl_4s3u_3: ok
Test: scopes -> ok
Passed gowin-adffs.ys
xprop_shr_4u3u_3: ok
xprop_ge_5u3_2: ok
xprop_shr_4u3u_3: ok
xprop_ge_5u3_2: ok
xprop_gt_5s3_2: ok
xprop_logic_not_3s_3: ok
xprop_gt_5s3_2: ok
Test: module_scope -> ok
xprop_logic_not_3s_3: ok
Test: mem_arst -> ok
Test: trans_sdp -> ok
Test: code_verilog_tutorial_explicit -> ok
xprop_neg_3s_5: ok
xprop_neg_3s_5: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: test_parse2synthtrans -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: implicit_ports -> ok
Checking notcnt1.aig.
Test: mem2reg_bounds_tern -> ok
xprop_reduce_bool_3s_1: ok
Test: omsp_dbg_uart -> ok
Test: i2c_master_tests -> ok
xprop_reduce_bool_3s_1: ok
[35]Passed various-muxcover.ys
xprop_ne_5u3_2: ok
xprop_ne_5u3_2: ok
Test: t_init_lut_zeros_zero -> ok
xprop_logic_or_3s3_3: ok
xprop_ff_1: ok
xprop_ff_1: ok
xprop_logic_or_3s3_3: ok
Test: t_sync_big -> ok
Test: muxtree -> ok
Test: realexpr -> ok
Test: paramods -> ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_dff_1pd: ok
Test: macros -> ok
Passed microchip-reduce.ys
xprop_dff_1pd: ok
K...passed tests in tests/liberty
Test: code_hdl_models_up_down_counter -> ok
Test: i2c_master_tests -> ok
xprop_sub_5s3_3: ok
xprop_logic_or_3u3_3: ok
xprop_shr_4s3u_3: ok
xprop_sub_5s3_3: ok
Test: muxtree -> ok
Kxprop_logic_or_3u3_3: ok
xprop_shr_4s3u_3: ok
Test: t_init_18b2B_val_any -> ok
xprop_reduce_and_3u_3: ok
xprop_reduce_and_3u_3: ok
xprop_bwmux_1: ok
xprop_bwmux_1: ok
xprop_logic_and_1u1_1: ok
Test: code_verilog_tutorial_comment -> ok
xprop_logic_and_1u1_1: ok
Kxprop_add_5u3_3: ok
xprop_reduce_bool_3u_3: ok
xprop_reduce_bool_3u_3: ok
xprop_add_5u3_3: ok
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
xprop_logic_and_3s3_1: ok
xprop_logic_and_3s3_1: ok
Test: values -> ok
[36]Passed memory_bram test 01_02.
Checking notcnt1e.aig.
Test: omsp_dbg_uart -> ok
xprop_reduce_xnor_3s_3: ok
xprop_shift_4u3u_3: ok
xprop_reduce_xnor_3s_3: ok
xprop_shift_4u3u_3: ok
xprop_shift_4s3s_3: ok
xprop_shift_4s3s_3: ok
xprop_not_3s_5: ok
xprop_logic_not_1u_1: ok
xprop_not_3s_5: ok
xprop_logic_not_1u_1: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
xprop_ne_5s3_2: ok
xprop_eqx_5s3_2: ok
xprop_ne_5s3_2: ok
xprop_dffe_1nnd: ok
xprop_dffe_1nnd: ok
Test: loops -> ok
Test: wide_all -> ok
Kxprop_eqx_5s3_2: ok
[37]Checking or_.aig.
xprop_sshr_4u3u_3: ok
xprop_nex_5u3_2: ok
Test: code_verilog_tutorial_decoder_always -> ok
Test: signed_full_slice -> ok
xprop_nex_5u3_2: ok
[38]xprop_sshr_4u3u_3: ok
Test: subbytes -> ok
xprop_eq_5s3_2: ok
xprop_eq_5s3_2: ok
Test: module_scope -> ok
xprop_pmux_2_2: ok
Test: code_specman_switch_fabric -> ok
xprop_pmux_2_2: ok
xprop_bweqx_3: ok
[39]xprop_bweqx_3: ok
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
Test: scopes -> ok
xprop_bmux_3_1: ok
KPassed sat-share.ys
xprop_mod_5s3_3: ok
xprop_bmux_3_1: ok
xprop_mod_5s3_3: ok
K[40]Passed nexus-counter.ys
Kxprop_divfloor_5s3_3: ok
xprop_divfloor_5s3_3: ok
xprop_bweqx_1: ok
xprop_bweqx_1: ok
[41]Passed various-ice40_mince_abc9.ys
xprop_reduce_or_3u_3: ok
xprop_reduce_or_3u_3: ok
xprop_ff_3: ok
xprop_ff_3: ok
Kxprop_shl_4u3u_3: ok
xprop_mod_5u3_3: ok
xprop_demux_1_2: ok
xprop_mod_5u3_3: ok
xprop_shl_4u3u_3: ok
xprop_dffe_1pnd: ok
Test: defvalue -> ok
xprop_demux_1_2: ok
xprop_dffe_1pnd: ok
Test: test_simulation_always -> ok
Test: func_width_scope -> ok
Test: wandwor -> ok
Test: subbytes -> ok
xprop_mux_1: ok
xprop_mux_1: ok
Passed gowin-mux.ys
Test: paramods -> ok
xprop_pmux_1_4: ok
Checking symbols.aig.
xprop_pmux_1_4: ok
xprop_sshl_4u3u_3: ok
xprop_sshl_4u3u_3: ok
xprop_logic_and_3s3_3: ok
Test: signedexpr -> ok
[42]xprop_logic_and_3s3_3: ok
Test: repwhile -> ok
Kxprop_dff_1nd: ok
[43]xprop_dff_1nd: ok
xprop_dff_3pd: ok
xprop_dff_3pd: ok
Test: hierdefparam -> ok
xprop_mul_5s3_3: ok
xprop_div_5u3_3: ok
xprop_mul_5s3_3: ok
xprop_div_5u3_3: ok
Test: dff_different_styles -> ok
Checking toggle.aig.
Test: test_simulation_sop -> ok
Test: t_sync_2clk_shared -> ok
[44]xprop_div_5s3_3: ok
xprop_div_5s3_3: ok
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
xprop_nex_5s3_2: ok
xprop_nex_5s3_2: ok
Test: mem2reg -> ok
xprop_mux_3: ok
Test: test_simulation_mux -> ok
xprop_mux_3: ok
Test: task_func -> ok
[45]xprop_demux_2_2: ok
xprop_demux_2_2: ok
Test: multiplier -> ok
[46]Checking toggle-re.aig.
Test: code_hdl_models_uart -> ok
[47]Test: fsm -> ok
xprop_shift_4s2s_8: ok
xprop_modfloor_5s3_3: ok
xprop_shift_4s2s_8: ok
xprop_shift_4s3u_3: ok
xprop_modfloor_5s3_3: ok
xprop_shift_4s3u_3: ok
[48]Test: vloghammer -> ok
xprop_shift_4u2s_8: ok
xprop_dffe_3ppd: ok
xprop_shift_4u2s_8: ok
xprop_dffe_3ppd: ok
Checking true.aig.
[49]xprop_add_5s3_3: ok
xprop_add_5s3_3: ok
xprop_demux_3_1: ok
xprop_pmux_4_4: ok
xprop_demux_3_1: ok
Kxprop_bmux_1_2: ok
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
xprop_pmux_4_4: ok
xprop_bmux_1_2: ok
Passed various-celledges_shift.ys
Test: issue00335 -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/memories'
Running io.ys.
Testing expectations for amber23_sram_byte_en.v ..Warning: reg '\out' is assigned in a continuous assignment at <<EOF:5.9-5.25.
xprop_mul_5u3_3: ok
Running neg.ys.
xprop_mul_5u3_3: ok
Test: loops -> ok
Test: repwhile -> ok
[50]Test: test_simulation_techmap -> ok
xprop_bwmux_3: ok
Test: values -> ok
xprop_sshr_4s3u_3: ok
xprop_bwmux_3: ok
[51]xprop_sshr_4s3u_3: ok
...passed tests in tests/aiger
Passed ice40-mux.ys
xprop_reduce_and_3s_3: ok
xprop_reduce_and_3s_3: ok
[52]K[53]Test: multiplier -> ok
Warning: Wire adffn.q has an unprocessed 'init' attribute.
[54]xprop_modfloor_5u3_3: ok
xprop_modfloor_5u3_3: ok
[55]Passed qlf_k6n10f-fsm.ys
xprop_pmux_3_1: ok
xprop_pmux_3_1: ok
 ok.
[56]Testing expectations for implicit_en.v ..Passed xilinx-shifter.ys
[57][58]Passed intel_alm-lutram.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/intel_alm'
...passed tests in tests/arch/intel_alm
Test: func_block -> ok
[59]xprop_shiftx_4u3s_3: ok
xprop_shiftx_4u3s_3: ok
Test: dff_different_styles -> ok
[60]Test: wandwor -> ok
K[61]Test: process -> ok
KTest: test_simulation_decoder -> ok
[62]K ok.
Testing expectations for issue00335.v ..[63]Test: mem_arst -> ok
Passed gatemate-latches.ys
Test: wreduce -> ok
[64]KWarning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits.
xprop_dffe_3pnd: ok
xprop_dffe_3pnd: ok
[65]KKWarning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits.
 ok.
Testing expectations for issue00710.v ..[66]Test: arrays03 -> ok
KTest: test_simulation_shifter -> ok
[67]K[68]Test: vloghammer -> ok
 ok.
Testing expectations for no_implicit_en.v ..[69]K[70][71]Passed gatemate-mux.ys
[72][73] ok.
Testing expectations for read_arst.v ..[74]KPassed xilinx-bug1605.ys
Test: dynslice -> ok
Test: task_func -> ok
xprop_dffe_1ppd: ok
xprop_dffe_1ppd: ok
done
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/xprop'
[75]...passed tests in tests/xprop
[76]K[77][78] ok.
Testing expectations for read_two_mux.v ..[79][80]Test: asgn_binop -> ok
Test: wreduce -> ok
K[81]Passed gowin-init.ys
K[82]Passed anlogic-blockram.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/anlogic'
...passed tests in tests/arch/anlogic
[83] ok.
Testing expectations for shared_ports.v ..Passed ecp5-adffs.ys
[84][85]Test: asgn_binop -> ok
[86]Passed xilinx-bug1480.ys
 ok.
Testing expectations for simple_sram_byte_en.v ..Warning: Shift register inference not yet supported for family xc3s.
[87][88]KTest: macro_arg_spaces -> ok
 ok.
Testing expectations for trans_addr_enable.v ..[89]Passed nexus-fsm.ys
K[90]Warning: Wire dffs.q has an unprocessed 'init' attribute.
[91][92] ok.
Testing expectations for trans_sdp.v ..[93][94] ok.
Testing expectations for trans_sp.v ..[95]K[96] ok.
Testing expectations for wide_all.v ..Test: rotate -> ok
[97]Test: constmuldivmod -> ok
Passed xilinx-dsp_fastfir.ys
[98][99]Passed ecp5-mux.ys
 ok.
Testing expectations for wide_read_async.v ..
K...passed tests in tests/share
KTest: generate -> ok
Passed xilinx-counter.ys
 ok.
Testing expectations for wide_read_mixed.v .. ok.
Testing expectations for wide_read_sync.v ..Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits.
...passed tests in tests/peepopt
 ok.
Testing expectations for wide_read_trans.v ..KPassed microchip-ram_TDP.ys
Passed nanoxplore-dffs.ys
 ok.
Testing expectations for wide_thru_priority.v ..Passed nanoxplore-logic.ys
KPassed ice40-adffs.ys
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2663: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_RDATA': Setting 18 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2709: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_RDATA': Setting 18 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Range [4:1] select out of bounds on signal `\PORT_A1_WR_BE': Setting 3 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_A1_WR_BE [1] } = 4'0000
    new assignment: \PORT_A1_WR_BE [1] = 1'0.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Range [3:0] select out of bounds on signal `\PORT_A1_WR_BE': Setting 2 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_A1_WR_BE } = \PORT_A1_WR_BE_i
    new assignment: \PORT_A1_WR_BE = \PORT_A1_WR_BE_i [1:0].
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Range [4:1] select out of bounds on signal `\PORT_B1_WR_BE': Setting 3 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_B1_WR_BE [1] } = 4'0000
    new assignment: \PORT_B1_WR_BE [1] = 1'0.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Range [3:0] select out of bounds on signal `\PORT_B1_WR_BE': Setting 2 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_B1_WR_BE } = \PORT_B1_WR_BE_i
    new assignment: \PORT_B1_WR_BE = \PORT_B1_WR_BE_i [1:0].
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Range [36:17] select out of bounds on signal `\PORT_A1_WDATA': Setting 19 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_A1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_A1_WDATA [17] = 1'0.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_WDATA': Setting 18 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_A1_WDATA } = \PORT_A1_WR_DATA_i
    new assignment: \PORT_A1_WDATA = \PORT_A1_WR_DATA_i [17:0].
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Range [36:17] select out of bounds on signal `\PORT_B1_WDATA': Setting 19 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_B1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_B1_WDATA [17] = 1'0.
Test: mem2reg -> ok
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_WDATA': Setting 18 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_B1_WDATA } = \PORT_B1_WR_DATA_i
    new assignment: \PORT_B1_WDATA = \PORT_B1_WR_DATA_i [17:0].
 ok.
Testing expectations for wide_write.v ..Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits.
Passed gatemate-mul.ys
 ok.
...passed tests in tests/memories
Passed qlf_k6n10f-latches.ys
KKTest: sincos -> ok
KPassed gatemate-adffs.ys
Test: sincos -> ok
KPassed xilinx-logic.ys
KPassed microchip-mult.ys
Passed microchip-widemux.ys
Test: test_simulation_techmap_tech -> ok
KPassed microchip-simple_ram.ys
Warning: Wire ndffnr.q has an unprocessed 'init' attribute.
Passed qlf_k6n10f-adffs.ys
Test: constmuldivmod -> ok
Test: abc9 -> ok
Passed xilinx-add_sub.ys
KPassed xilinx-bug1598.ys
Test: t_sync_big_lut -> ok
KTest: memory -> ok
Test: t_async_big -> ok
Warning: Shift register inference not yet supported for family xc3se.
Warning: Wire TB.\rq_b [35] is used but has no driver.
Warning: Wire TB.\rq_b [34] is used but has no driver.
Warning: Wire TB.\rq_b [33] is used but has no driver.
Warning: Wire TB.\rq_b [32] is used but has no driver.
Warning: Wire TB.\rq_b [31] is used but has no driver.
Warning: Wire TB.\rq_b [30] is used but has no driver.
Warning: Wire TB.\rq_b [29] is used but has no driver.
Warning: Wire TB.\rq_b [28] is used but has no driver.
Warning: Wire TB.\rq_b [27] is used but has no driver.
Warning: Wire TB.\rq_b [26] is used but has no driver.
Warning: Wire TB.\rq_b [25] is used but has no driver.
Warning: Wire TB.\rq_b [24] is used but has no driver.
Warning: Wire TB.\rq_b [23] is used but has no driver.
Warning: Wire TB.\rq_b [22] is used but has no driver.
Warning: Wire TB.\rq_b [21] is used but has no driver.
Warning: Wire TB.\rq_b [20] is used but has no driver.
Warning: Wire TB.\rq_b [19] is used but has no driver.
Warning: Wire TB.\rq_b [18] is used but has no driver.
Warning: Wire TB.\rq_b [17] is used but has no driver.
Warning: Wire TB.\rq_b [16] is used but has no driver.
Warning: Wire TB.\rq_b [15] is used but has no driver.
Warning: Wire TB.\rq_b [14] is used but has no driver.
Warning: Wire TB.\rq_b [13] is used but has no driver.
Warning: Wire TB.\rq_b [12] is used but has no driver.
Warning: Wire TB.\rq_b [11] is used but has no driver.
Warning: Wire TB.\rq_b [10] is used but has no driver.
Warning: Wire TB.\rq_b [9] is used but has no driver.
Warning: Wire TB.\rq_b [8] is used but has no driver.
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Passed nexus-dffs.ys
Test: test_intermout -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/hana'
...passed tests in tests/hana
Passed nexus-logic.ys
Passed xilinx-xilinx_dffopt.ys
Test: operators -> ok
Passed xilinx-tribuf.ys
Test: t_async_big_block -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/memlib'
...passed tests in tests/memlib
+ ./yosys-always_full
+ iverilog -o iverilog-always_full always_full.v always_full_tb.v
+ ./iverilog-always_full
+ grep -v '\$finish called'
+ diff iverilog-always_full.log yosys-always_full.log
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits.
+ test_cxxrtl always_comb
+ local subtest=always_comb
+ shift
+ ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' --

1. Executing Verilog-2005 frontend: always_comb.v
Parsing Verilog input from `always_comb.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\sub'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$always_comb.v:3$13'.
  Set init value: \b = 1'0
Found init rule in `\top.$proc$always_comb.v:2$12'.
  Set init value: \a = 1'0

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\sub.$proc$always_comb.v:23$15'.
     1/1: $display$always_comb.v:23$19_EN
Creating decoders for process `\top.$proc$always_comb.v:3$13'.
Creating decoders for process `\top.$proc$always_comb.v:2$12'.
Creating decoders for process `\top.$proc$always_comb.v:8$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$22' with positive edge clock.
Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$23' with positive edge clock.

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'.
Removing empty process `sub.$proc$always_comb.v:23$15'.
Removing empty process `top.$proc$always_comb.v:3$13'.
Removing empty process `top.$proc$always_comb.v:2$12'.
Removing empty process `top.$proc$always_comb.v:8$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module sub.
Optimizing module top.
Removed 0 unused cells and 7 unused wires.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
root of   0 design levels: sub                 
root of   1 design levels: top                 
Automatically selected top as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub

3.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub
Removed 0 unused modules.
Module sub directly or indirectly displays text -> setting "keep" attribute.
Module top directly or indirectly displays text -> setting "keep" attribute.

3.2. Executing FLATTEN pass (flatten design).
Deleting now unused module sub.
<suppressed ~1 debug messages>

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

<suppressed ~12 debug messages>

End of script. Logfile hash: a6b3c2e895, CPU: user 0.01s system 0.00s, MEM: 12.43 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 31% 2x opt_expr (0 sec), 16% 1x clean (0 sec), ...
+ gcc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++
Passed nexus-add_sub.ys
KPassed ice40-macc.ys
Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
KTest: generate -> ok
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [35] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [34] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [33] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [32] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [31] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [30] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [29] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [28] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [27] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [26] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [25] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [24] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [23] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [22] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [21] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [20] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [19] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [18] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [17] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [16] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [15] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [14] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [13] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [12] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [11] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [10] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [9] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [8] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:514:run$18023 [7] is used but has no driver.
Passed nanoxplore-add_sub.ys
Passed xilinx-bug1460.ys
Passed xilinx-macc.sh
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed qlf_k6n10f-dsp.ys
KPassed memory_bram test 02_01.
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/bram'
...passed tests in tests/bram
Warning: Resizing cell port pre_post_adder.$mul$<<EOT:8$746.A from 6 bits to 18 bits.
K+ ./yosys-always_comb
+ iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v
+ grep -v '\$finish called'
+ ./iverilog-always_comb
+ diff iverilog-always_comb.log yosys-always_comb.log
+ ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog always_full.v; prep; clean' --

1. Executing Verilog-2005 frontend: always_full.v
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).
Module always_full directly or indirectly displays text -> setting "keep" attribute.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
Removed 0 unused cells and 207 unused wires.
<suppressed ~1 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \always_full..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \always_full.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.7.8. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).
Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits.

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits.
Finding unused cells or wires in module \always_full..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== always_full ===

   Number of wires:                  1
   Number of wire bits:              1
   Number of public wires:           1
   Number of public wire bits:       1
   Number of ports:                  1
   Number of port bits:              1
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                207
     $print                        207

2.13. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.

-- Writing to `yosys-always_full-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\always_full'.

End of script. Logfile hash: 52e889d7da, CPU: user 0.03s system 0.01s, MEM: 13.85 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 20% 4x opt_clean (0 sec), 15% 1x prep (0 sec), ...
+ iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v
Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits.
Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits.
+ ./iverilog-always_full-1
+ grep -v '\$finish called'
+ diff iverilog-always_full.log iverilog-always_full-1.log
+ ../../yosys -p 'read_verilog display_lm.v'
Test: case_large -> ok
+ ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' --

1. Executing Verilog-2005 frontend: display_lm.v
Parsing Verilog input from `display_lm.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\mid'.
Generating RTLIL representation for module `\bot'.
%l: \bot
%m: \bot
Successfully finished Verilog frontend.

2. Executing CXXRTL backend.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Finding top of design hierarchy..
root of   0 design levels: bot                 
root of   1 design levels: mid                 
root of   2 design levels: top                 
Automatically selected top as design top module.

2.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot

2.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot
Removed 0 unused modules.
Module bot directly or indirectly displays text -> setting "keep" attribute.
Module mid directly or indirectly displays text -> setting "keep" attribute.
Module top directly or indirectly displays text -> setting "keep" attribute.

2.2. Executing FLATTEN pass (flatten design).
Deleting now unused module bot.
Deleting now unused module mid.
<suppressed ~2 debug messages>

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 2 redundant assignments.
Promoted 2 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).

2.3.5. Executing PROC_ARST pass (detect async resets in processes).

2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
Cleaned up 0 empty switches.

2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

<suppressed ~12 debug messages>

End of script. Logfile hash: 15a147f3a6, CPU: user 0.01s system 0.00s, MEM: 11.94 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 33% 1x opt_expr (0 sec), 18% 2x read_verilog (0 sec), ...
+ gcc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
Passed qlf_k6n10f-mux.ys
Test: code_hdl_models_cam -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/asicworld'
...passed tests in tests/asicworld
Passed xilinx-bug1462.ys
Passed xilinx-mul.ys
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Passed ecp5-lutram.ys
Test: rotate -> ok
Warning: Complex async reset for dff `\Q'.
Test: memory -> ok
Passed qlf_k6n10f-div.ys
+ ./yosys-display_lm_cc
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm.log
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm.log
%m: \bot
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm_cc.log
%l: \bot
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm_cc.log
%m: \bot
%m: \bot
...passed tests in tests/fmt
Passed xilinx-nosrl.ys
Passed various-pmgen_reduce.ys
Passed xilinx-tribuf.sh
Passed nexus-tribuf.ys
Passed xilinx-dsp_simd.ys
Passed nexus-shifter.ys
Passed ice40-dpram.ys
Passed nexus-lutram.ys
Warning: Resizing cell port mac.$mul$<<EOT:13$1121.A from 5 bits to 18 bits.
Test: operators -> ok
Passed xilinx-macc.ys
Passed nexus-blockram.ys
Test: dynslice -> ok
Warning: Drivers conflicting with a constant 1'0 driver:
    module input PORT_A1_WR_BE_i[1]
    module input PORT_A1_WR_DATA_i[17]
    module input PORT_B1_WR_BE_i[1]
    module input PORT_B1_WR_DATA_i[17]
Passed nanoxplore-adffs.ys
Passed xilinx-fsm.ys
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits.
Passed sat-clk2fflogic.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/sat'
...passed tests in tests/sat
Passed microchip-ram_SDP.ys
Warning: Resizing cell port cas.$mul$<<EOT:11$1502.A from 6 bits to 18 bits.
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed techmap-booth.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/techmap'
...passed tests in tests/techmap
Passed nanoxplore-mux.ys
Passed machxo2-lutram.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/machxo2'
...passed tests in tests/arch/machxo2
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/usr/local/google/home/cannada/Software/yosys/yosys/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Warning: Ignoring boxed module $paramod\FDRE\INIT=1'0_$abc9_flop.
Passed verilog-func_upto.ys
Test: partsel -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/simple'
...passed tests in tests/simple
Passed nanoxplore-latches.ys
KK
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/fsm'
...passed tests in tests/fsm
Passed xilinx-dsp_abc9.ys
Passed ice40-bug1644.ys
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits.
Warning: Selection "asym_ram_sdp_read_wider" did not match any module.
Passed qlf_k6n10f-meminit.ys
Passed gatemate-memory.ys
Passed xilinx-mux_lut4.ys
Passed nexus-mux.ys
Passed xilinx-pmgen_xilinx_srl.ys
Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Passed xilinx-latches.ys
Passed nexus-mul.ys
Passed xilinx-mul_unsigned.ys
Passed microchip-dff.ys
Passed xilinx-mux.ys
Warning: Resizing cell port pipeline.$mul$<<EOT:69$2265.A from 6 bits to 18 bits.
Passed microchip-dsp.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/microchip'
...passed tests in tests/arch/microchip
Passed xilinx-adffs.ys
Passed gatemate-luttrees.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/gatemate'
...passed tests in tests/arch/gatemate
Passed nanoxplore-meminit.ys
Passed nexus-adffs.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/nexus'
...passed tests in tests/arch/nexus
Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits.
Passed xilinx-dffs.ys
Test: case_large -> ok
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits.
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/opt_share'

...passed tests in tests/opt_share
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits.
Passed xilinx-attributes_test.ys
Passed nanoxplore-lutram.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/nanoxplore'
...passed tests in tests/arch/nanoxplore
Passed qlf_k6n10f-ioff.ys
Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits.
Passed xilinx-asym_ram_sdp.ys
Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_A from 8 bits to 9 bits.
Warning: Resizing cell port sp_read_or_write.mem.0.0.BWE_B from 8 bits to 9 bits.
Passed xilinx-priority_memory.ys
Passed verilog-dynamic_range_lhs.sh
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/verilog'
...passed tests in tests/verilog
Passed qlf_k6n10f-t_mem6.ys
Passed qlf_k6n10f-t_mem4.ys
Passed qlf_k6n10f-t_mem5.ys
Passed qlf_k6n10f-t_mem3.ys
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[0] --> Y[0]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[0] --> Q[0]
    wire \dword [0] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[0] --> Y[0]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[1] --> Y[1]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[1] --> Q[1]
    wire \dword [1] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[1] --> Y[1]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[2] --> Y[2]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[2] --> Q[2]
    wire \dword [2] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[2] --> Y[2]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[3] --> Y[3]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[3] --> Q[3]
    wire \dword [3] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[3] --> Y[3]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[4] --> Y[4]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[4] --> Q[4]
    wire \dword [4] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[4] --> Y[4]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[5] --> Y[5]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[5] --> Q[5]
    wire \dword [5] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[5] --> Y[5]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[6] --> Y[6]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[6] --> Q[6]
    wire \dword [6] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[6] --> Y[6]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[7] --> Y[7]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[7] --> Q[7]
    wire \dword [7] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[7] --> Y[7]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[8] --> Y[8]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[8] --> Q[8]
    wire \dword [8] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[8] --> Y[8]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[9] --> Y[9]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[9] --> Q[9]
    wire \dword [9] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[9] --> Y[9]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[10] --> Y[10]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[10] --> Q[10]
    wire \dword [10] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[10] --> Y[10]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[11] --> Y[11]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[11] --> Q[11]
    wire \dword [11] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[11] --> Y[11]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[12] --> Y[12]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[12] --> Q[12]
    wire \dword [12] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[12] --> Y[12]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[13] --> Y[13]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[13] --> Q[13]
    wire \dword [13] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[13] --> Y[13]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[14] --> Y[14]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[14] --> Q[14]
    wire \dword [14] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[14] --> Y[14]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[15] --> Y[15]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[15] --> Q[15]
    wire \dword [15] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[15] --> Y[15]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[16] --> Y[16]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[16] --> Q[16]
    wire \dword [16] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[16] --> Y[16]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[17] --> Y[17]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[17] --> Q[17]
    wire \dword [17] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[17] --> Y[17]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[18] --> Y[18]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[18] --> Q[18]
    wire \dword [18] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[18] --> Y[18]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[19] --> Y[19]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[19] --> Q[19]
    wire \dword [19] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[19] --> Y[19]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[20] --> Y[20]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[20] --> Q[20]
    wire \dword [20] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[20] --> Y[20]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[21] --> Y[21]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[21] --> Q[21]
    wire \dword [21] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[21] --> Y[21]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[22] --> Y[22]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[22] --> Q[22]
    wire \dword [22] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[22] --> Y[22]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[23] --> Y[23]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[23] --> Q[23]
    wire \dword [23] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[23] --> Y[23]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[24] --> Y[24]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[24] --> Q[24]
    wire \dword [24] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[24] --> Y[24]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[25] --> Y[25]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[25] --> Q[25]
    wire \dword [25] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[25] --> Y[25]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[26] --> Y[26]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[26] --> Q[26]
    wire \dword [26] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[26] --> Y[26]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[27] --> Y[27]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[27] --> Q[27]
    wire \dword [27] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[27] --> Y[27]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[28] --> Y[28]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[28] --> Q[28]
    wire \dword [28] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[28] --> Y[28]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[29] --> Y[29]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[29] --> Q[29]
    wire \dword [29] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[29] --> Y[29]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[30] --> Y[30]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[30] --> Q[30]
    wire \dword [30] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[30] --> Y[30]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[31] --> Y[31]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[31] --> Q[31]
    wire \dword [31] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[31] --> Y[31]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[32] --> Y[32]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[32] --> Q[32]
    wire \dword [32] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[32] --> Y[32]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[33] --> Y[33]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[33] --> Q[33]
    wire \dword [33] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[33] --> Y[33]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[34] --> Y[34]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[34] --> Q[34]
    wire \dword [34] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[34] --> Y[34]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[35] --> Y[35]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[35] --> Q[35]
    wire \dword [35] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[35] --> Y[35]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[36] --> Y[36]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[36] --> Q[36]
    wire \dword [36] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[36] --> Y[36]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[37] --> Y[37]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[37] --> Q[37]
    wire \dword [37] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[37] --> Y[37]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[38] --> Y[38]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[38] --> Q[38]
    wire \dword [38] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[38] --> Y[38]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[39] --> Y[39]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[39] --> Q[39]
    wire \dword [39] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[39] --> Y[39]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[40] --> Y[40]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[40] --> Q[40]
    wire \dword [40] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[40] --> Y[40]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[41] --> Y[41]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[41] --> Q[41]
    wire \dword [41] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[41] --> Y[41]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[42] --> Y[42]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[42] --> Q[42]
    wire \dword [42] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[42] --> Y[42]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[43] --> Y[43]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[43] --> Q[43]
    wire \dword [43] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[43] --> Y[43]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[44] --> Y[44]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[44] --> Q[44]
    wire \dword [44] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[44] --> Y[44]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[45] --> Y[45]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[45] --> Q[45]
    wire \dword [45] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[45] --> Y[45]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[46] --> Y[46]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[46] --> Q[46]
    wire \dword [46] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[46] --> Y[46]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[47] --> Y[47]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[47] --> Q[47]
    wire \dword [47] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[47] --> Y[47]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[48] --> Y[48]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[48] --> Q[48]
    wire \dword [48] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[48] --> Y[48]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[49] --> Y[49]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[49] --> Q[49]
    wire \dword [49] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[49] --> Y[49]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[50] --> Y[50]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[50] --> Q[50]
    wire \dword [50] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[50] --> Y[50]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[51] --> Y[51]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[51] --> Q[51]
    wire \dword [51] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[51] --> Y[51]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[52] --> Y[52]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[52] --> Q[52]
    wire \dword [52] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[52] --> Y[52]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[53] --> Y[53]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[53] --> Q[53]
    wire \dword [53] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[53] --> Y[53]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[54] --> Y[54]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[54] --> Q[54]
    wire \dword [54] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[54] --> Y[54]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[55] --> Y[55]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[55] --> Q[55]
    wire \dword [55] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[55] --> Y[55]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[56] --> Y[56]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[56] --> Q[56]
    wire \dword [56] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[56] --> Y[56]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[57] --> Y[57]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[57] --> Q[57]
    wire \dword [57] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[57] --> Y[57]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[58] --> Y[58]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[58] --> Q[58]
    wire \dword [58] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[58] --> Y[58]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[59] --> Y[59]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[59] --> Q[59]
    wire \dword [59] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[59] --> Y[59]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[60] --> Y[60]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[60] --> Q[60]
    wire \dword [60] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[60] --> Y[60]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[61] --> Y[61]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[61] --> Q[61]
    wire \dword [61] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[61] --> Y[61]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[62] --> Y[62]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[62] --> Q[62]
    wire \dword [62] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[62] --> Y[62]
Warning: found logic loop in module latch_002_gate:
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[63] --> Y[63]
    cell $auto$proc_dlatch.cc:432:proc_dlatch$13483 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[63] --> Q[63]
    wire \dword [63] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[63] --> Y[63]
Passed qlf_k6n10f-t_mem2.ys
Passed gowin-lutram.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/gowin'
...passed tests in tests/arch/gowin
Warning: Shift register inference not yet supported for family xc3s.
Randomized tests for value::shl:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::shr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sshr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::add:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sub:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::ctlz:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::udivmod (div):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::udivmod (mod):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sdivmod (div):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sdivmod (mod):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
+ ../../yosys -p 'read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2025  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)

-- Running command `read_verilog test_unconnected_output.v; select =*; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' --

1. Executing Verilog-2005 frontend: test_unconnected_output.v
Parsing Verilog input from `test_unconnected_output.v' to AST representation.
Generating RTLIL representation for module `\blackbox'.
Generating RTLIL representation for module `\unconnected_output'.
test_unconnected_output.v:19: Warning: Identifier `\clock' is implicitly declared.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Warning: Ignoring boxed module blackbox.
Optimizing module unconnected_output.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
Warning: Ignoring boxed module blackbox.
root of   1 design levels: unconnected_output  
Automatically selected unconnected_output as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \unconnected_output

3.1.3. Analyzing design hierarchy..
Top module:  \unconnected_output
Removed 0 unused modules.
Warning: Resizing cell port unconnected_output.bb.out1 from 1 bits to 8 bits.

3.2. Executing FLATTEN pass (flatten design).

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Warning: Ignoring boxed module blackbox.
Optimizing module unconnected_output.

<suppressed ~20 debug messages>

Warnings: 3 unique messages, 5 total
End of script. Logfile hash: 5ce3cff38f, CPU: user 0.01s system 0.00s, MEM: 12.01 MB peak
Yosys 0.55+109 (git sha1 2223d7848, clang-19 19.1.7 -fPIC -O3)
Time spent: 28% 2x opt_expr (0 sec), 14% 1x clean (0 sec), ...
+ gcc -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc
Passed various-dynamic_part_select.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/various'
...passed tests in tests/various
...passed tests in tests/cxxrtl
Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits.
Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits.
Passed xilinx-lutram.ys
Passed xilinx-abc9_dff.ys
Passed ecp5-memories.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/ecp5'
...passed tests in tests/arch/ecp5
Passed qlf_k6n10f-t_mem1.ys
Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits.
Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits.
Passed xilinx-blockram.ys
Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits.
Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits.
Passed qlf_k6n10f-t_mem0.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/quicklogic/qlf_k6n10f'
...passed tests in tests/arch/quicklogic/qlf_k6n10f
Passed ice40-memories.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/ice40'
...passed tests in tests/arch/ice40
Passed xilinx-dsp_cascade.ys
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/arch/xilinx'
...passed tests in tests/arch/xilinx
Test: partsel -> ok
make[1]: Leaving directory '/usr/local/google/home/cannada/Software/yosys/yosys/tests/simple_abc9'
...passed tests in tests/simple_abc9
rm tests/sat/run-test.mk tests/arch/quicklogic/pp3/run-test.mk tests/arch/anlogic/run-test.mk tests/arch/efinix/run-test.mk tests/arch/microchip/run-test.mk tests/arch/ice40/run-test.mk tests/arch/gowin/run-test.mk tests/arch/machxo2/run-test.mk tests/arch/quicklogic/qlf_k6n10f/run-test.mk tests/opt/run-test.mk tests/arch/intel_alm/run-test.mk tests/various/run-test.mk tests/arch/nanoxplore/run-test.mk tests/verilog/run-test.mk tests/arch/nexus/run-test.mk tests/sim/run-test.mk tests/arch/gatemate/run-test.mk tests/arch/ecp5/run-test.mk tests/svtypes/run-test.mk tests/arch/xilinx/run-test.mk tests/techmap/run-test.mk