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aiju/docs_gvpack_fix

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docs-previewtest

resources

v0.48

v0.49

v0.50

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yosys-0.10

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yosys-0.3.0

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ed0e2f7a6f Added log_assert() api Clifford Wolf 2013-05-24 14:38:36 +02:00
ccd2a93439 Added log_abort() api Clifford Wolf 2013-05-24 12:32:06 +02:00
585fcace10 Fixed a gcc vs. clang determinism problem in abc pass Clifford Wolf 2013-05-23 16:17:23 +02:00
f674150f1c Fixed memory corruption bug in opt_rmunused Clifford Wolf 2013-05-23 13:19:28 +02:00
cbe423a1fe Only initialize TCL interpreter when needed Clifford Wolf 2013-05-23 12:56:23 +02:00
375f83c5ec Fixed memory leak in ilang frontend Clifford Wolf 2013-05-23 12:55:59 +02:00
e04d88cf22 Added missing newline to some error messages Clifford Wolf 2013-05-23 11:19:33 +02:00
6a38e767ba Added labels to "help -write-tex-command-reference-manual" output Clifford Wolf 2013-05-23 09:49:37 +02:00
ebb155b2d5 Added support for processes to show command Clifford Wolf 2013-05-23 09:15:51 +02:00
04996657c8 Fixed show command for constant assignments Clifford Wolf 2013-05-23 08:22:44 +02:00
3b8882ae49 Some improvements in opt_rmdff Clifford Wolf 2013-05-23 07:48:18 +02:00
63e6a35ce2 Merge pull request #6 from hansiglaser/master Clifford Wolf 2013-05-19 16:07:55 -07:00
2d95e58dc7 Merge 10a195c0a1 into fbadb54b9b Johann Glaser 2013-05-19 08:10:23 -07:00
10a195c0a1 added option '-Dname[=definition]' to command 'read_verilog' Johann Glaser 2013-05-19 17:07:52 +02:00
fbadb54b9b Removed test cases that have been moved to yosys-test. Clifford Wolf 2013-05-17 15:32:30 +02:00
3ecc314238 Fixed to aggressive x-folding in opt_const Clifford Wolf 2013-05-17 14:55:18 +02:00
59d0c75b98 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-05-16 16:51:47 +02:00
c5ee2b306a Merge branch 'bugfix' Clifford Wolf 2013-05-16 16:44:45 +02:00
6cc8e848b6 Fixed synthesis of functions in latched blocks Clifford Wolf 2013-05-16 16:44:06 +02:00
ff4a1dd06c Improved vcdcd.pl (added -d option) Clifford Wolf 2013-05-14 09:41:47 +02:00
be8ecd6d16 Some improvements in vcdcd.pl Clifford Wolf 2013-05-14 08:50:59 +02:00
b56e06d2f5 Added support for verilog === operator Clifford Wolf 2013-05-07 14:35:40 +02:00
595db0d7b9 Added tcl "yosys -import" command Clifford Wolf 2013-05-02 15:27:01 +02:00
97f783e668 Improved/simplified TCL bindings Clifford Wolf 2013-05-01 14:21:03 +02:00
83c743f717 Added support for const cell inputs in techmap Clifford Wolf 2013-04-27 18:30:29 +02:00
7d0a274f12 Fixed README for new show command behavior (svg vs. ps) Clifford Wolf 2013-04-27 14:41:46 +02:00
b1cb4d7871 Added "flatten" pass Clifford Wolf 2013-04-26 14:40:45 +02:00
8f2d90de4f Fixed handling of positional module parameters Clifford Wolf 2013-04-26 14:40:25 +02:00
94744ac7b0 Fixed hierarchy pass for hierarchies of parametric modules Clifford Wolf 2013-04-26 13:28:15 +02:00
453a29c9f6 Only use sha1 checksums for names of parametric modules when the verbose form is to long Clifford Wolf 2013-04-26 13:13:58 +02:00
e6dca3445a Fixed "show -format ..." command line parsing Clifford Wolf 2013-04-15 11:59:35 +02:00
6626aad29a Added "submod -name ..." support Clifford Wolf 2013-04-15 11:58:24 +02:00
e0c408cb4a Fixed a bug in AST frontend for cases with non-blocking assigned variables as case values Clifford Wolf 2013-04-13 21:19:10 +02:00
c6198ea5a8 Fixed a bug in opt_const when optimizing 1-bit compares with constants Clifford Wolf 2013-04-13 21:18:24 +02:00
db10275251 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-04-07 16:42:38 +02:00
32dbf7752d Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v Clifford Wolf 2013-04-07 16:42:29 +02:00
00a877e09b Merge pull request #5 from hansiglaser/master Clifford Wolf 2013-04-05 07:04:51 -07:00
fc317fff3d Merge 7ef245aa7d into ab74706338 Johann Glaser 2013-04-05 06:36:13 -07:00
7ef245aa7d fsm_export: optionally use binary state encoding as state names instead of s0, s1, ... Johann Glaser 2013-04-05 15:34:40 +02:00
ab74706338 Merge pull request #4 from hansiglaser/master Clifford Wolf 2013-04-05 02:30:44 -07:00
09ea60bf7d Merge 9714072b28 into af4444e5b9 Johann Glaser 2013-04-05 02:19:42 -07:00
9714072b28 fsm_export: specify KISS filename on command line Johann Glaser 2013-04-05 11:17:49 +02:00
af4444e5b9 Fixed/improved handling of colored wires in show command Clifford Wolf 2013-04-01 14:58:43 +02:00
32ee794bfb Added support for @<set-name> in expand select ops (%x, %ci, %co) Clifford Wolf 2013-04-01 14:58:11 +02:00
5919bf5525 Removed 4096 bytes limit for size of command from script file Clifford Wolf 2013-04-01 14:38:05 +02:00
3ec9fa4048 Added -color <color> <selection> option to show command Clifford Wolf 2013-04-01 14:12:17 +02:00
9b1ce98db6 Fixed "select" for "%%" stmt with emty stack Clifford Wolf 2013-03-31 18:06:27 +02:00
b66e9fb348 Added "script" command Clifford Wolf 2013-03-31 18:05:31 +02:00
f1a2fd966f Now only use value from "initial" when no matching "always" block is found Clifford Wolf 2013-03-31 11:51:12 +02:00
161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) Clifford Wolf 2013-03-31 11:19:11 +02:00
5640b7d607 Added test cases from 2012 paper on comparison of foss verilog synthesis tools Clifford Wolf 2013-03-31 11:17:56 +02:00
04843bdcbe Added k68 (m68k compatible cpu) test case from verilator Clifford Wolf 2013-03-31 11:00:46 +02:00
88af5b6a16 Improved opt_share for reduce cells Clifford Wolf 2013-03-29 11:19:21 +01:00
0d48b846ac Improved opt_share for commutative standard cells Clifford Wolf 2013-03-29 11:01:26 +01:00
d60fbaf664 Added EXTRA_TARGETS Makefile variable Clifford Wolf 2013-03-28 16:53:40 +01:00
eff8c68dd9 Improved Makefile: Added ENABLE_* switches Clifford Wolf 2013-03-28 16:50:50 +01:00
73fba5164f Implemented TCL support (only via -c option at the moment) Clifford Wolf 2013-03-28 12:26:17 +01:00
b9870a364e Improved subcircuit verbose output (added portmapper results) Clifford Wolf 2013-03-28 11:36:54 +01:00
c46597b697 Fixed svgviewer hacks for builtin files Clifford Wolf 2013-03-28 10:47:35 +01:00
8edf4f378a Added proper TECHMAP_FAIL support and added support for the celltype attribute in the map file Clifford Wolf 2013-03-28 10:12:50 +01:00
7bfc7b61a8 Implemented proper handling of stub placeholder modules Clifford Wolf 2013-03-28 09:20:10 +01:00
98fcb5daa3 Keep viewport transform stable on reload in yosys-svgviewer Clifford Wolf 2013-03-27 18:48:38 +01:00
92cf7ae2f7 Added check: only one module for "show" unless format is "ps" Clifford Wolf 2013-03-27 18:31:42 +01:00
35a02ee81e Now using SVG and yosys-svgviewer per default in show command Clifford Wolf 2013-03-27 18:14:16 +01:00
9c401b58a2 Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib Clifford Wolf 2013-03-27 10:51:15 +01:00
62b9e16f87 Imported svgviewer from qt4.8 Clifford Wolf 2013-03-27 06:57:57 +01:00
041c06bd9d Create nice errors when calling RTLIL::Module::derive() of base class Clifford Wolf 2013-03-26 19:27:49 +01:00
6a231816fa Collect parameters in hierarchy -generate (and do nothing with them) Clifford Wolf 2013-03-26 19:11:53 +01:00
26f2439551 Tiny bugfix in simlib.v Clifford Wolf 2013-03-26 19:06:28 +01:00
7a99349de4 Improvements and bugfixes for generate blocks with local signals Clifford Wolf 2013-03-26 11:13:58 +01:00
6a382f2aba Fixed handling of unconditional generate blocks Clifford Wolf 2013-03-26 09:44:54 +01:00
227520f94d Added nosync attribute and some async reset related fixes Clifford Wolf 2013-03-25 17:13:14 +01:00
3737964809 Improved verbose output of subcircuit Clifford Wolf 2013-03-25 11:08:52 +01:00
0f5378b559 Improved method for finding fsm_expand candidates Clifford Wolf 2013-03-25 02:24:11 +01:00
4a7d624bef Added hierarchy -generate command for generating skeletton modules Clifford Wolf 2013-03-25 02:14:33 +01:00
4bd6f1ee8e Changed fsm_expand to merge multiplexers more aggressively Clifford Wolf 2013-03-24 17:59:44 +01:00
d9bc024d29 Renamed hansimem.v test case to mem_arst.v Clifford Wolf 2013-03-24 15:25:08 +01:00
e1a80b356e Fixed handling of show -viewer Clifford Wolf 2013-03-24 15:21:57 +01:00
2887e4305f Fixed handling of internal signals in show command Clifford Wolf 2013-03-24 15:15:28 +01:00
181b479e77 Improved show -colors color assignments Clifford Wolf 2013-03-24 13:32:56 +01:00
bbae24bdf7 Added show -strech and renamed -widthlabels to -width Clifford Wolf 2013-03-24 13:27:04 +01:00
f921b06fb0 Added -widthlabels options to chow command Clifford Wolf 2013-03-24 13:11:06 +01:00
05ae20f260 Added -notypes option to intersynth backend Clifford Wolf 2013-03-24 12:05:25 +01:00
8cc1c87ab8 Reorganized TODOs Clifford Wolf 2013-03-24 11:23:54 +01:00
df9753d398 Added mem2reg option to verilog frontend Clifford Wolf 2013-03-24 11:13:32 +01:00
6960df7285 Fixed stdcells.v for $adff with undef reset value Clifford Wolf 2013-03-24 10:43:05 +01:00
3a5244e913 Another fix in mem2reg ast simplify logic Clifford Wolf 2013-03-24 10:42:08 +01:00
55c50dc499 Added -colors option to show command Clifford Wolf 2013-03-24 10:41:24 +01:00
c3c9e5a02f Added hansimem testcase (memory with async reset) Clifford Wolf 2013-03-24 10:40:40 +01:00
bb3357c027 Improved mem2reg handling in ast simplifier Clifford Wolf 2013-03-24 09:27:01 +01:00
a0fa259d81 Fixed gcc build (intersynth backend) Clifford Wolf 2013-03-23 19:01:58 +01:00
e45d1c8865 Tiny fixes to verilog parser Clifford Wolf 2013-03-23 18:54:31 +01:00
bee57c808a Various improvements in intersynth backend Clifford Wolf 2013-03-23 12:02:09 +01:00
80aefb3eaa Added intersynth backend Clifford Wolf 2013-03-23 10:58:14 +01:00
47325fb271 Added help -write-tex-command-reference-manual option Clifford Wolf 2013-03-21 11:33:56 +01:00
69ce1191c0 Added eclipse CDT project files to .gitignore Clifford Wolf 2013-03-21 10:59:35 +01:00
8f610dca58 Added -S option for simple synthesis to gate logic Clifford Wolf 2013-03-21 09:52:21 +01:00
87c7717566 Avoid verilog-2k in verilog backend Clifford Wolf 2013-03-21 09:51:25 +01:00
91b94ef57b Disabled the per-default dumping of ILANG code Clifford Wolf 2013-03-21 09:12:32 +01:00
8d37d1e08b Added -nomap option to memory pass Clifford Wolf 2013-03-21 09:11:06 +01:00