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yosys-0.4

yosys-0.40

yosys-0.41

yosys-0.42

yosys-0.43

yosys-0.44

yosys-0.5

yosys-0.6

yosys-0.7

yosys-0.8

yosys-0.9

Mono Color

• 4007b41d40 Improved xilinx mojo_counter example Clifford Wolf 2013-10-26 22:28:42 +0200
• ceb971eab9 Added support for i/o buffers to iopadmap Clifford Wolf 2013-10-26 22:27:40 +0200
• b934a2d209 Added another xilinx example (not funcional yet) Clifford Wolf 2013-10-26 17:22:29 +0200
• dd56004fc0 Added support for sr flip-flops to dfflibmap Clifford Wolf 2013-10-24 18:20:06 +0200
• 628b994cf6 Added support for complex set-reset flip-flops in proc_dff Clifford Wolf 2013-10-24 16:54:05 +0200
• e679a5d046 Fixed handling of boolean attributes (passes) Clifford Wolf 2013-10-24 11:37:54 +0200
• e9dede01ca Fixed handling of boolean attributes (backends) Clifford Wolf 2013-10-24 11:27:30 +0200
• 23cf23418c Fixed handling of boolean attributes (frontends) Clifford Wolf 2013-10-24 11:20:13 +0200
• eae43e2db4 Fixed handling of boolean attributes (kernel) Clifford Wolf 2013-10-24 10:59:27 +0200
• 77726fb5fe Fixed parsing of value-less attributes in ilang Clifford Wolf 2013-10-23 18:38:31 +0200
• d61699843f Improved handling of dff with async resets Clifford Wolf 2013-10-21 14:51:58 +0200
• 56ea230676 Added handling of multiple async paths in proc_arst Clifford Wolf 2013-10-19 00:50:13 +0200
• 8e8f1994b8 Changed NEW_WIRE API to return the wire, not the signal Clifford Wolf 2013-10-18 14:19:45 +0200
• bfa1a65fa9 Added dffsr support to proc_dff pass Clifford Wolf 2013-10-18 13:26:52 +0200
• cc5e379eca Added RTLIL NEW_WIRE macro Clifford Wolf 2013-10-18 13:25:24 +0200
• 0836a1f2ba Bugfix in dffsr techmap rules Clifford Wolf 2013-10-18 13:24:44 +0200
• 8197169f8d Added techmap rules for $sr, $dffsr and $dlatch Clifford Wolf 2013-10-18 12:29:21 +0200
• e0f693cbb0 Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_ Clifford Wolf 2013-10-18 12:13:34 +0200
• 5998c101a4 Added $sr, $dffsr and $dlatch cell types Clifford Wolf 2013-10-18 11:56:16 +0200
• 9bc703b964 Improved way of connecting ports in techmap pass Clifford Wolf 2013-10-17 22:19:38 +0200
• 8cc53ef72c Only prefer connected signals iff they have public names Clifford Wolf 2013-10-17 22:10:55 +0200
• 30b0de006f Added -buf, -true and -false options to blif backend Clifford Wolf 2013-10-17 21:37:18 +0200
• 95dbacefbf Fixed bug in synthesis of memories that are never written Clifford Wolf 2013-10-17 21:00:37 +0200
• c20571ca5e Avoid re-arranging signals on register outputs Clifford Wolf 2013-10-17 20:48:40 +0200
• f5c0ed6c79 Fixed detection of major wires in opt_clean Clifford Wolf 2013-10-17 02:41:59 +0200
• 96e7abad48 Added iopadmap pass Clifford Wolf 2013-10-16 16:16:06 +0200
• b6db2d9b33 Moved dfflibmap from passes/dfflibmap to passes/techmap Clifford Wolf 2013-10-16 15:32:26 +0200
• 5745d3de9a Added map, par and bitgen to xlinx7 example Clifford Wolf 2013-10-16 10:57:18 +0200
• 845590aa8e Fixed parsing or liberty file statements such as 'clocked_on : "(!CLK)";' Patch by Tim Edwards Clifford Wolf 2013-10-16 06:32:35 +0200
• a12d39bc86 Added recommended apt-get commands to README Clifford Wolf 2013-10-11 22:25:23 +0200
• a97520785a Fixed minisat include Clifford Wolf 2013-10-11 21:17:01 +0200
• 02efafa7f1 Pinned ABC revision to 0f9e5488ced3 Clifford Wolf 2013-10-03 16:03:30 +0200
• 5dce6379aa Improvements in EDIF backend Clifford Wolf 2013-09-17 13:07:12 +0200
• dc767d4e4c Added additional options to BLIF backend Clifford Wolf 2013-09-15 13:33:33 +0200
• 0ec5542ab4 Added BLIF backend Clifford Wolf 2013-09-15 13:13:01 +0200
• 28069e8a10 A couple of small fixes in SPICE backend Clifford Wolf 2013-09-15 12:19:06 +0200
• 288ba9618a Moved common techlib files to techlibs/common Clifford Wolf 2013-09-15 11:52:57 +0200
• 647c23b7b7 Updated manual Clifford Wolf 2013-09-15 11:41:05 +0200
• 2c9bd23801 Added spice testbench to techlibs/cmos Clifford Wolf 2013-09-14 13:29:11 +0200
• bbe5aa446b Added spice backend Clifford Wolf 2013-09-14 11:23:45 +0200
• 70476e2431 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2013-09-03 19:10:25 +0200
• 73914d1a41 Added -selected option to various backends Clifford Wolf 2013-09-03 19:10:11 +0200
• 09e200797a Encode large (>32 bits) parameters as hex string in edif backend Clifford Wolf 2013-08-28 08:48:49 +0200
• 2feee7415d Improved edif backend Clifford Wolf 2013-08-27 14:22:11 +0200
• 6685ad436e Added mapping to techlibs/xilinx7 testbench (exposes EDIF backend todos) Clifford Wolf 2013-08-27 13:12:26 +0200
• 5059b31660 Added simple xilinx7 technology mapping files Clifford Wolf 2013-08-22 20:26:19 +0200
• 39ee561169 More explicit integer output in verilog backend Clifford Wolf 2013-08-22 20:22:19 +0200
• 4f4cb2307f Added correct encoding of identifiers in EDIF backend Clifford Wolf 2013-08-22 14:30:33 +0200
• aba8639a3f Added edif backend (still under construction) Clifford Wolf 2013-08-22 11:34:55 +0200
• 8409956c0c Merge pull request #10 from hansiglaser/master Clifford Wolf 2013-08-21 09:47:06 -0700
• 93f7ff820a Merge f352205635 into f8107ab7fc Johann Glaser 2013-08-21 09:46:32 -0700
• f8107ab7fc Some minor documentation fixes Clifford Wolf 2013-08-21 12:16:44 +0200
• f352205635 fixed Verilog parser filename and line numbering issue with include files Johann Glaser 2013-08-21 09:20:59 +0200
• 459e8964fd Merge pull request #9 from hansiglaser/master Clifford Wolf 2013-08-20 09:38:31 -0700
• 0d6dff388b Merge a99c224157 into 8e31a92407 Johann Glaser 2013-08-20 06:50:09 -0700
• a99c224157 Added support for include directories with the new '-I' argument of the 'read_verilog' command Johann Glaser 2013-08-20 15:48:16 +0200
• 8e31a92407 Merge pull request #8 from hansiglaser/master Clifford Wolf 2013-08-20 03:36:34 -0700
• 7aadad36d6 Merge 6c4cbc03c2 into e3aa0514f2 Johann Glaser 2013-08-20 02:26:01 -0700
• 6c4cbc03c2 Added support for notif0/notif1 primitives Johann Glaser 2013-08-20 11:23:59 +0200
• e3aa0514f2 Added cleaning of old version_* files to version_* make rule Clifford Wolf 2013-08-20 10:12:54 +0200
• 485e870bcd Added version info to yosys command and added -V option Clifford Wolf 2013-08-20 09:48:12 +0200
• 1af1cebb64 Minor fixes in abc build instructions and abc pass Clifford Wolf 2013-08-20 09:46:05 +0200
• 0003743432 Fixed width and sign detection for ** operator Clifford Wolf 2013-08-19 20:58:01 +0200
• 8656b1c08f Added support for bufif0/bufif1 primitives Clifford Wolf 2013-08-19 19:50:04 +0200
• 4214561890 Improved ast dumping (ast/verilog frontend) Clifford Wolf 2013-08-19 19:49:14 +0200
• a860efa8ac Implemented same div-by-zero behavior as found in other synthesis tools Clifford Wolf 2013-08-15 21:00:06 +0200
• 78658199e6 Fixed signed div/mod in const eval (rounding and stuff) Clifford Wolf 2013-08-15 18:23:42 +0200
• 457dc09cdc Added ezsat api for creation of anonymous vectors Clifford Wolf 2013-08-15 14:40:26 +0200
• 2f3da54f26 Added sat -ignore_div_by_zero switch Clifford Wolf 2013-08-15 11:40:01 +0200
• d0e93e04d1 Added eval -brute_force_equiv_checker_x mode Clifford Wolf 2013-08-15 11:09:30 +0200
• 759852914d Added support for "2**n" shifter encoding Clifford Wolf 2013-08-12 14:47:50 +0200
• ccf36cb7d8 Added SAT support for $div and $mod cells Clifford Wolf 2013-08-11 16:27:15 +0200
• a5836af172 Added "clean -purge" and ";;;" support Clifford Wolf 2013-08-11 13:59:14 +0200
• 080f0aac34 Added ";;" as shortcut for "; clean;" Clifford Wolf 2013-08-11 13:33:38 +0200
• 6068b8902f freduce performance fix Clifford Wolf 2013-08-10 15:03:13 +0200
• c8763301b4 Added $div and $mod technology mapping Clifford Wolf 2013-08-09 17:09:24 +0200
• 376150c926 Added techmap -opt mode Clifford Wolf 2013-08-09 15:20:22 +0200
• 05483619f0 Some fixes to improve determinism Clifford Wolf 2013-08-09 12:42:32 +0200
• d97782b848 Sort ctrl signals in fsm_extract Clifford Wolf 2013-08-08 15:46:00 +0200
• 6a40e46a04 Added -try option to freduce pass Clifford Wolf 2013-08-08 10:56:27 +0200
• 8cd153612e Added "clean" command (less verbose opt_clean) Clifford Wolf 2013-08-08 10:53:37 +0200
• 56e01ce389 Fixed topological ordering in freduce pass Clifford Wolf 2013-08-07 19:38:19 +0200
• e729857647 Improved handling of private names in opt_clean and rename commands Clifford Wolf 2013-08-07 18:39:49 +0200
• 3f5d7df603 Added stubnets example to manual prog chapter Clifford Wolf 2013-08-07 02:19:35 +0200
• 653750faac Small bugfixes in freduce pass Clifford Wolf 2013-08-06 15:53:09 +0200
• 6efca9ea5a Added freduce command Clifford Wolf 2013-08-06 15:04:52 +0200
• 117489f95a Fixed SigPool::del() method Clifford Wolf 2013-08-06 15:04:24 +0200
• ff965424c2 Added proper deallocation of history buffer Clifford Wolf 2013-08-06 15:03:46 +0200
• 8b2f7792ba Updated TODO section in README Clifford Wolf 2013-08-01 20:02:15 +0200
• 0f38008ed3 Added "design" command (-reset, -save, -load) Clifford Wolf 2013-07-27 14:27:51 +0200
• 974b6a947c Added "help -write-web-command-reference-manual" Clifford Wolf 2013-07-26 00:01:31 +0200
• 98906b211c Fixed comments in manual rtlil/ilang syntax Clifford Wolf 2013-07-25 15:01:02 +0200
• 36c39cbd04 Added RTLIL and Liberty syntax highlighting to manual Clifford Wolf 2013-07-25 14:00:16 +0200
• 88d0829d65 Automatically run "proc" on extract map files Clifford Wolf 2013-07-24 20:19:08 +0200
• ad9bbcbf40 Added $lut cells and abc lut mapping support Clifford Wolf 2013-07-23 16:19:34 +0200
• d815f1c770 Fixed "make clean" for manual files Clifford Wolf 2013-07-23 14:19:47 +0200
• 3bb1996151 Added web site link to README Clifford Wolf 2013-07-21 15:04:37 +0200
• 61ed6b32d1 Added Yosys Manual Clifford Wolf 2013-07-20 15:19:12 +0200
• 3650fd7fbe More fixes in ternary op sign handling Clifford Wolf 2013-07-12 13:13:04 +0200
• ded769c98c Fixed sign handling in ternary operator Clifford Wolf 2013-07-12 01:15:37 +0200