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yosys-0.4

yosys-0.40

yosys-0.41

yosys-0.42

yosys-0.43

yosys-0.44

yosys-0.5

yosys-0.6

yosys-0.7

yosys-0.8

yosys-0.9

Mono Color

• 078cecf9ea Updated todo items in README file Clifford Wolf 2014-02-05 01:59:30 +0100
• aa9da46807 Removed old unused files from tests/ Clifford Wolf 2014-02-05 01:55:39 +0100
• 968ae31cac Added support for dump -append Clifford Wolf 2014-02-04 23:45:30 +0100
• 1fb8ba73bd Throw errors if non-existing selection variables are used Clifford Wolf 2014-02-04 23:31:06 +0100
• b1bf55dd63 Added select -none Clifford Wolf 2014-02-04 23:23:44 +0100
• e0c867db53 presentation progress Clifford Wolf 2014-02-04 23:00:48 +0100
• 99b9c56da1 Fixed detection of init attribute in opt_rmdff Clifford Wolf 2014-02-04 23:00:32 +0100
• 69e867f3e8 Added support for inline commands to abc -script Clifford Wolf 2014-02-04 22:01:53 +0100
• 03d63dd861 presentation progress Clifford Wolf 2014-02-04 16:51:12 +0100
• 7a5f378bae Added hierarchy -purge_lib option Clifford Wolf 2014-02-04 16:50:13 +0100
• 7a66b38c3e Added test cases for sat command Clifford Wolf 2014-02-04 13:43:34 +0100
• 6891fd79a3 added sat -falsify Clifford Wolf 2014-02-04 13:34:37 +0100
• d267bcde4e Fixed bug in sequential sat proofs and improved handling of asserts Clifford Wolf 2014-02-04 12:46:16 +0100
• ecdf1f5577 Improved handling of reg init in opt_share and opt_rmdff Clifford Wolf 2014-02-04 12:02:47 +0100
• 9e938aa32a presentation progress Clifford Wolf 2014-02-04 00:57:11 +0100
• 6c3d767976 presentation progress Clifford Wolf 2014-02-03 16:26:27 +0100
• 9e35021585 Addred sat option -ignore_unknown_cells Clifford Wolf 2014-02-03 16:26:10 +0100
• a6750b3753 Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem) Clifford Wolf 2014-02-03 13:01:45 +0100
• de9226a64f Replaced isim with xsim in tests/tools/autotest.sh, removed xst support Clifford Wolf 2014-02-03 13:00:55 +0100
• de336d93b2 More opt_const -mux_bool features Clifford Wolf 2014-02-02 22:41:24 +0100
• 982c9da011 presentation progress Clifford Wolf 2014-02-02 22:26:26 +0100
• 9d0b69edaa Added opt_const -mux_bool Clifford Wolf 2014-02-02 22:11:08 +0100
• bee4450c4c Added support for inverter chains to opt_const Clifford Wolf 2014-02-02 21:46:42 +0100
• f9c4d33909 Added RTLIL::SigSpec::to_single_sigbit() Clifford Wolf 2014-02-02 21:35:26 +0100
• 67b0ce2578 Only generate write-enable $and if WE is not constant 1 in memory_map Clifford Wolf 2014-02-02 21:27:26 +0100
• 83fa652820 Added constant-clock case to opt_rmdff Clifford Wolf 2014-02-02 21:09:08 +0100
• 6983d3f10b presentation progress Clifford Wolf 2014-02-02 17:57:14 +0100
• aa732b0c73 Added show -notitle option Clifford Wolf 2014-02-02 17:55:32 +0100
• 9808acdc75 Added delete command Clifford Wolf 2014-02-02 17:11:19 +0100
• a9e2d86f86 Added suuport for module attribute matching with A:<pattern>[=<pattern>] syntax Clifford Wolf 2014-02-02 16:47:17 +0100
• 0f88e28693 presentation progress Clifford Wolf 2014-02-02 13:30:49 +0100
• 9334c34170 presentation progress Clifford Wolf 2014-02-02 13:06:28 +0100
• cdd6e11af5 Added support for blanks after -I and -D in read_verilog Clifford Wolf 2014-02-02 13:06:21 +0100
• f4f0bd6eef Fixed a bug in miter command Clifford Wolf 2014-02-01 22:53:27 +0100
• 374674aff4 Added sat -show-inputs and -show-outputs Clifford Wolf 2014-02-01 22:52:44 +0100
• caf540d1ad Added show -color support for cells and finished show -label implementation Clifford Wolf 2014-02-01 18:23:32 +0100
• af325bf206 Fixed comment/eol parsing in ilang frontend Clifford Wolf 2014-02-01 17:28:02 +0100
• d06258f74f Added constant size expression support of sized constants Clifford Wolf 2014-02-01 13:50:23 +0100
• 1e2440e7ed Added note about SystemVerilog assert statement to README Clifford Wolf 2014-02-01 13:04:49 +0100
• fa92722358 Added miter command Clifford Wolf 2014-02-01 10:35:56 +0100
• 1c8f6f21b4 Progress on presentation Clifford Wolf 2014-01-31 12:48:31 +0100
• ed8ad99960 More changes to techlibs/common/simlib.v for LEC Clifford Wolf 2014-01-31 11:21:29 +0100
• 36a808c572 presentation progress Clifford Wolf 2014-01-30 15:25:09 +0100
• 4df7e03ec9 Bugfix in name resolution with generate blocks Clifford Wolf 2014-01-30 14:52:46 +0100
• 672229eda5 Added yosys -H for command list Clifford Wolf 2014-01-30 12:32:59 +0100
• 34b39ec28a presentation progress Clifford Wolf 2014-01-29 15:56:58 +0100
• cbe77bf844 presentation progress Clifford Wolf 2014-01-29 12:15:38 +0100
• aceab5fc08 Tiny change in example script in README Clifford Wolf 2014-01-29 11:11:10 +0100
• 96084e9864 Added -h command line option Clifford Wolf 2014-01-29 11:10:39 +0100
• 6a7d7e847d Added test comments to techlibs/cmos/cmos_cells.lib Clifford Wolf 2014-01-29 10:51:02 +0100
• c46b23ab23 Updated ABC to hg rev e6b09e1 Clifford Wolf 2014-01-29 10:50:15 +0100
• 375c4dddc1 Added read_verilog -icells option Clifford Wolf 2014-01-29 00:59:28 +0100
• a86f33653d Major rewrite of techlibs/common/simlib.v for LEC (cadance conformal) Clifford Wolf 2014-01-29 00:36:03 +0100
• 961b791272 presentation progress Clifford Wolf 2014-01-28 20:28:22 +0100
• 2cb47355d4 Renamed manual/FILES_* directories Clifford Wolf 2014-01-28 06:55:47 +0100
• 842ca2f011 Progress on presentation Clifford Wolf 2014-01-28 06:51:50 +0100
• a3ac6b6f47 Progress on presentation Clifford Wolf 2014-01-27 20:42:35 +0100
• fb4c3dff33 Added first presentation slides Clifford Wolf 2014-01-27 17:08:19 +0100
• fa103e55ad Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys Clifford Wolf 2014-01-26 02:29:19 +0100
• fd6ca84f3c Merge pull request #21 from hansiglaser/master Clifford Wolf 2014-01-25 17:28:17 -0800
• e9a2094774 enabled multiple "-map" for the extract pass Johann Glaser 2014-01-25 21:11:34 +0100
• f13b3518aa beautified write_intersynth Johann Glaser 2014-01-25 20:16:38 +0100
• 0325efe172 root bug corrected Ahmed Irfan 2014-01-25 19:33:24 +0100
• c1ed2607fb Added support for // comments in liberty parser Clifford Wolf 2014-01-25 06:32:16 +0100
• a139b49401 Merge branch 'btor' Clifford Wolf 2014-01-24 23:44:46 +0100
• 137742786e removed regex include Ahmed Irfan 2014-01-24 18:04:37 +0100
• 2e44b1b73a merged clifford changes + removed regex Ahmed Irfan 2014-01-24 17:35:42 +0100
• 210dda286f Use techmap -share_map in btor scripts Clifford Wolf 2014-01-24 15:52:16 +0100
• 6804edd5d4 Moved btor scripts to backends/btor/ Clifford Wolf 2014-01-24 15:48:07 +0100
• da26bb4378 Restored Makefile Clifford Wolf 2014-01-24 15:47:09 +0100
• ec167350b4 Restored IdString::check() Clifford Wolf 2014-01-24 15:46:41 +0100
• d8300d1fb8 Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor Clifford Wolf 2014-01-24 15:43:42 +0100
• 0b47d907d3 Fixed handling of unsized constants in verilog frontend Clifford Wolf 2014-01-24 15:05:24 +0100
• 761b8f99d7 minor change in script Ahmed Irfan 2014-01-24 15:00:43 +0100
• 9d07d83c5a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-01-22 10:45:21 +0100
• 88fbdd4916 Fixed algorithmic complexity of AST simplification of long expressions Clifford Wolf 2014-01-20 20:25:20 +0100
• aa3cb20e1e slice bug corrected Ahmed Irfan 2014-01-20 18:35:52 +0100
• c347f2825f assert feature Ahmed Irfan 2014-01-20 10:45:02 +0100
• b7adf4c7a0 Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-01-20 09:58:04 +0100
• 32a91458a7 Added hilomap command Clifford Wolf 2014-01-19 21:58:58 +0100
• 03a876c7e8 Added sat -tempinduc and sat -prove-asserts Clifford Wolf 2014-01-19 15:38:23 +0100
• c36bac0e10 Added $assert support to satgen Clifford Wolf 2014-01-19 15:37:56 +0100
• 1e67099b77 Added $assert cell Clifford Wolf 2014-01-19 14:03:40 +0100
• 9a1eb45c75 Added Verilog parser support for asserts Clifford Wolf 2014-01-19 04:18:22 +0100
• 234d0d0e1c script added Ahmed Irfan 2014-01-18 21:54:52 +0100
• 90483f489b Merge branch 'master' of https://github.com/ahmedirfan1983/yosys into btor Ahmed Irfan 2014-01-18 19:45:16 +0100
• 3d7a1491aa Fixed $lut simlib model for a wider range of tools Clifford Wolf 2014-01-18 19:27:16 +0100
• 13359d65ba Fixed parsing of verilog macros at end of line Clifford Wolf 2014-01-18 19:22:20 +0100
• 2fbaaaca7a More changes to simlib to make it friendlier to a wider range of tools Clifford Wolf 2014-01-18 19:13:43 +0100
• 4a9e133fab Fixed a type in $mem model in simlib.v Clifford Wolf 2014-01-18 18:54:50 +0100
• b281e13263 Merge branch 'master' of https://github.com/ahmedirfan1983/yosys Ahmed Irfan 2014-01-18 18:11:26 +0100
• 1dd797ab09 Merge branch 'master' of https://github.com/cliffordwolf/yosys Ahmed Irfan 2014-01-18 18:10:31 +0100
• da8af91552 pmux2mux Ahmed Irfan 2014-01-18 17:29:55 +0100
• bef17eeb10 Removed cases of trailing comma in stdcells.v Clifford Wolf 2014-01-18 15:36:17 +0100
• 5b96675696 Added $bu0 cell to simlib.v Clifford Wolf 2014-01-18 15:35:15 +0100
• 839af272ad Improved setundef random number generator Clifford Wolf 2014-01-18 02:56:36 +0100
• 091d9abc3e Added setundef command Clifford Wolf 2014-01-17 23:14:36 +0100
• 548d5aafa4 Some improvements in log_dump_val_worker() templates Clifford Wolf 2014-01-17 23:14:17 +0100
• db9cf544b8 Added techlibs/common/pmux2mux.v Clifford Wolf 2014-01-17 20:06:15 +0100
• 9a689f33a5 verilog default options pull shift operator width issues Ahmed Irfan 2014-01-17 19:32:35 +0100