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Commit graph

  • 623a68f528 Added iopadmap -bits Clifford Wolf 2014-02-15 21:59:26 +0100
  • 118517ca5a Added ff and latch support to read_liberty Clifford Wolf 2014-02-15 19:36:33 +0100
  • 96b1ebc8dc Bugfix in expression parser of read_liberty Clifford Wolf 2014-02-15 19:36:09 +0100
  • cdf0f10760 Fixed dfflibmap for cell libraries with no set-reset-ff Clifford Wolf 2014-02-15 16:34:12 +0100
  • 5e39e6ece2 Correctly convert constants to RTLIL (fixed undef handling) Clifford Wolf 2014-02-15 15:42:10 +0100
  • 30379ea20d Added frontend (-f) option to autotest.sh Clifford Wolf 2014-02-15 15:40:17 +0100
  • 67effc9f5b Fixed opt_const handling of double invert with non-1 output width Clifford Wolf 2014-02-15 13:16:08 +0100
  • 4440610d3f Added liberty frontend Clifford Wolf 2014-02-15 12:57:28 +0100
  • 45d2b6ffce Be more conservative with new const-function code Clifford Wolf 2014-02-14 20:45:30 +0100
  • e8af3def7f Added support for FOR loops in function calls in parameters Clifford Wolf 2014-02-14 20:33:22 +0100
  • 534c1a5dd0 Created basic support for function calls in parameter values Clifford Wolf 2014-02-14 19:56:44 +0100
  • 3121d19d95 Added abc -keepff option Clifford Wolf 2014-02-14 11:28:42 +0100
  • de3ea9269a updated default ABC command strings Clifford Wolf 2014-02-13 19:14:15 +0100
  • a123941618 Updated ABC Clifford Wolf 2014-02-13 18:56:36 +0100
  • cd9e8741a7 Implemented read_verilog -defer Clifford Wolf 2014-02-13 13:59:13 +0100
  • b463907890 Removed double blanks in ABC default command sequences Clifford Wolf 2014-02-13 08:12:52 +0100
  • c6236c9e97 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-13 08:09:17 +0100
  • 7664f5d92b Updated ABC and some related changes Clifford Wolf 2014-02-13 08:07:08 +0100
  • 6b210d2b6f Merge pull request #26 from ahmedirfan1983/btor Clifford Wolf 2014-02-12 23:46:58 +0100
  • 08caa631dd Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-12 23:30:02 +0100
  • 007bdff55d Added support for functions returning integer Clifford Wolf 2014-02-12 23:29:54 +0100
  • ac896c63e2 modified btor synthesis script for correct use of splice command. Ahmed Irfan 2014-02-12 13:38:28 +0100
  • 9ce7b0fc3b Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC) Clifford Wolf 2014-02-12 13:11:58 +0100
  • ab71bd0746 Updated ABC to rev e97a6e1d59b9 Clifford Wolf 2014-02-12 08:35:42 +0100
  • 0defc86519 renamed ilang "scope error" to "ilang error" Clifford Wolf 2014-02-11 19:17:07 +0100
  • 45e468114a disabling splice command in the script Ahmed Irfan 2014-02-11 15:43:03 +0100
  • 1d64b3e008 register output corrected Ahmed Irfan 2014-02-11 13:28:05 +0100
  • 1a2dc48c2a Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor Ahmed Irfan 2014-02-11 13:26:43 +0100
  • e8f6b8f201 added concat and slice cell translation Ahmed Irfan 2014-02-11 13:06:01 +0100
  • d2fd45949d More Makefile cleanups Clifford Wolf 2014-02-11 12:58:08 +0100
  • 4bd2d47e45 Improved "make manual" and "make clean" Clifford Wolf 2014-02-11 12:55:58 +0100
  • fb186e6299 Improved ilang parser error messages Clifford Wolf 2014-02-09 15:35:31 +0100
  • d229324420 fixed a bug in subcircuit library with cells that have connections to itself Clifford Wolf 2014-02-09 15:27:58 +0100
  • 38469e7686 Various improvements in expose command (added -sep and -cut) Clifford Wolf 2014-02-09 11:07:46 +0100
  • b6f33576d5 Added delete {-input|-output|-port} Clifford Wolf 2014-02-09 10:03:26 +0100
  • b3b5fac191 Bugfix in delete command Clifford Wolf 2014-02-09 09:34:58 +0100
  • 039bb456cc Added test cases for expose -evert-dff Clifford Wolf 2014-02-08 21:27:04 +0100
  • 85914c36e5 Fixed handling of async reset in expose -evert-dff Clifford Wolf 2014-02-08 21:26:40 +0100
  • db86aaa07d Build fixes for log cmd Clifford Wolf 2014-02-08 21:21:51 +0100
  • c06de50f05 Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-08 21:08:46 +0100
  • 0935e20003 Implemented expose -evert-dff Clifford Wolf 2014-02-08 21:08:38 +0100
  • 793290a304 Merge pull request #24 from hansiglaser/master Clifford Wolf 2014-02-08 20:02:32 +0100
  • af14bb5f65 added "log" command Johann Glaser 2014-02-08 19:19:32 +0100
  • 8f9c707a4c Improved checking of internal cell conventions Clifford Wolf 2014-02-08 19:13:49 +0100
  • 7f52c18a22 Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect Clifford Wolf 2014-02-08 19:13:19 +0100
  • 926fa61119 Added various new options to splice command Clifford Wolf 2014-02-08 16:37:18 +0100
  • 0c11d04144 Added %a select operator Clifford Wolf 2014-02-08 16:31:38 +0100
  • 6644f80d97 Moved some passes to other source directories Clifford Wolf 2014-02-08 14:39:15 +0100
  • 03ee63ff80 Added support for "keep" attribute to abc pass Clifford Wolf 2014-02-08 14:25:29 +0100
  • 82c98bbbe6 Added opt -purge (frontend to opt_clean -purge) Clifford Wolf 2014-02-08 14:21:34 +0100
  • 922d1c9520 Only count non-trivial attributes when findinf master signal in opt_clean Clifford Wolf 2014-02-08 14:21:04 +0100
  • 669a6e462d Added checking for ABC modifications to Makefile and made sure we do not have the word ERROR in regular make output Clifford Wolf 2014-02-08 12:27:38 +0100
  • 2c51619c2b Now also move net labes to the right position in splice cmd Clifford Wolf 2014-02-08 00:06:00 +0100
  • 274bcef66c Improved detection of primary wire for a signal in opt_clean Clifford Wolf 2014-02-07 23:50:17 +0100
  • 244e8ce1f4 Added splice command Clifford Wolf 2014-02-07 20:26:40 +0100
  • 08aa1062b4 Added log_header() to splitnets Clifford Wolf 2014-02-07 19:51:15 +0100
  • d85a6bf5d3 Added $slice and $concat to CellTypes list Clifford Wolf 2014-02-07 19:50:44 +0100
  • fc3b3c4ec3 Added $slice and $concat cell types Clifford Wolf 2014-02-07 17:44:57 +0100
  • a1ac710ab8 Stronger checking of internal cells Clifford Wolf 2014-02-07 17:39:35 +0100
  • 99b1e9ee56 Re-enabled abc "retime" after sorting yout the yosys-bigsim problem Clifford Wolf 2014-02-07 16:36:37 +0100
  • a51a3fa2d2 Added echo command Clifford Wolf 2014-02-07 14:17:00 +0100
  • 366dcd3abf Fixed use of "cmd_error" in passes/cmds/design.cc Clifford Wolf 2014-02-07 14:16:42 +0100
  • f4f230d7cc Fixed gcc compiler warnings with release build Clifford Wolf 2014-02-06 22:49:14 +0100
  • 0192f1c66e Disabled ABC retime for now (elliptic_curve_group testcase in yosys-bigsim failed) Clifford Wolf 2014-02-06 22:31:58 +0100
  • a170d114a5 Updated ABC to rev 10cc13a2a0f1 Clifford Wolf 2014-02-06 22:18:17 +0100
  • 58cb8d65af Added "retime" to standard ABC recipes Clifford Wolf 2014-02-06 22:16:20 +0100
  • 91eab69912 Added copy command Clifford Wolf 2014-02-06 22:09:21 +0100
  • cf593222f2 Added design -stash/-copy-from/-copy-to Clifford Wolf 2014-02-06 21:52:07 +0100
  • 37fdb2ca7a Added support for s: select expressions (wire width) Clifford Wolf 2014-02-06 19:45:03 +0100
  • 9428050dd6 Added i:, o:, and x: selection pattern Clifford Wolf 2014-02-06 19:35:33 +0100
  • d7d1c7baf8 Added support for %m selection op Clifford Wolf 2014-02-06 19:30:08 +0100
  • f2fdcef13d Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-06 19:22:50 +0100
  • fa295a4528 Added generic RTLIL::SigSpec::parse_sel() with support for selection variables Clifford Wolf 2014-02-06 19:22:46 +0100
  • 9c24b41f55 Merge pull request #23 from hansiglaser/master Clifford Wolf 2014-02-06 18:08:02 +0100
  • 34eb77d2bf new %s: add sub-modules to selection Johann Glaser 2014-02-06 17:36:39 +0100
  • d4b0f28881 Added support for sat -show @<sel_name> Clifford Wolf 2014-02-06 17:32:51 +0100
  • b1a12c5f37 Added sat -set-init-def and sat -tempinduct-def Clifford Wolf 2014-02-06 16:15:23 +0100
  • 594d52e0b6 Added opt_const -undriven Clifford Wolf 2014-02-06 15:49:03 +0100
  • c526e56747 Added expose -dff Clifford Wolf 2014-02-06 15:48:42 +0100
  • 1c6dea3a0d Added support for #-comments in same line as command Clifford Wolf 2014-02-06 14:26:39 +0100
  • 821156b6cf presentation progress Clifford Wolf 2014-02-06 14:01:43 +0100
  • c13c5b9b7b Changed techmap description from "simple" to "generic" Clifford Wolf 2014-02-06 13:10:06 +0100
  • eb8fd4a163 Added miter -make_outcmp Clifford Wolf 2014-02-06 02:20:55 +0100
  • 80a1cdb0e2 Added sat -set-init-zero support Clifford Wolf 2014-02-06 01:40:01 +0100
  • 19029f377b Added support for backslash continuation in script files Clifford Wolf 2014-02-06 01:28:33 +0100
  • 849fd62cfe Added counters sat test case Clifford Wolf 2014-02-06 01:00:11 +0100
  • e915043144 Added sat -verify and -falsify support for non-prove cases Clifford Wolf 2014-02-06 00:59:41 +0100
  • cd06055e77 Added expose command Clifford Wolf 2014-02-05 23:59:55 +0100
  • 7e9ba60df8 presentation progress Clifford Wolf 2014-02-05 20:06:34 +0100
  • dbfcc2f4e2 Simplified select "Assertation failed" message generation Clifford Wolf 2014-02-05 18:52:55 +0100
  • 94b802c65d Merge branch 'master' of github.com:cliffordwolf/yosys Clifford Wolf 2014-02-05 18:46:47 +0100
  • 7ea97a0471 Merge pull request #22 from hansiglaser/master Clifford Wolf 2014-02-05 18:46:36 +0100
  • 583636f0ad Added BTOR backend README file Clifford Wolf 2014-02-05 18:31:10 +0100
  • f6e6e9b844 Added selection support for r: and selection with relational operators Clifford Wolf 2014-02-05 18:24:45 +0100
  • 3c0b5139a1 be more verbose for select -assert-any and -assert-none Johann Glaser 2014-02-05 16:03:02 +0100
  • 667543de0b improved help for "select" Johann Glaser 2014-02-05 15:53:02 +0100
  • 3b5c462273 presentation progress Clifford Wolf 2014-02-05 15:06:13 +0100
  • 9f6364c1c4 presentation progress Clifford Wolf 2014-02-05 13:12:50 +0100
  • aa8e754ae5 Added read_verilog -setattr Clifford Wolf 2014-02-05 11:22:10 +0100
  • 5bf33de24a Added setattr and setparam commands Clifford Wolf 2014-02-05 11:11:55 +0100